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Interrupts

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Interrupts

The interrupt system of the STM32W108 is composed of two parts:

●

A standard ARM® Cortex-M3 Nested Vectored Interrupt Controller (NVIC) that

provides top level interrupts

●

An Event Manager (EM) that provides second level interrupts.

The NVIC and EM provide a simple hierarchy. All second level interrupts from the EM feed

into top level interrupts in the NVIC. This two level hierarchy allows for both fine granular

control of interrupt sources and coarse granular control over all peripherals, while allowing

the peripherals to have their own interrupt vector.

In practice, top level peripheral interrupts are only used to enable or disable interrupts for an

entire peripheral. Second level interrupts originate from hardware sources, and therefore are

the main focus of applications using interrupts.

12.1

Nested vectored interrupt controller (NVIC)

The ARM® Cortex-M3 Nested Vectored Interrupt Controller (NVIC) facilitates low-latency

exception and interrupt handling. The NVIC and the processor core interface are closely

coupled, which enables low-latency interrupt processing and efficient processing of late

arriving interrupts. The NVIC also maintains knowledge of the stacked (nested) interrupts to

enable tail-chaining of interrupts.

The ARM® Cortex-M3 NVIC contains 10 standard interrupts that are related to chip and

CPU operation and management. In addition to the 10 standard interrupts, it contains 17

individually vectored peripheral interrupts specific to the STM32W108.

The NVIC defines a list of exceptions (see Table 43). These exceptions include not only

traditional peripheral interrupts, but also more specialized events such as faults and CPU

reset. In the ARM® Cortex-M3 NVIC, a CPU reset event is considered an exception of the

highest priority, and the stack pointer is loaded from the first position in the NVIC exception

table. The NVIC exception table defines all exceptions and their position, including

peripheral interrupts. The position of each exception is important since it directly translates

to the location of a 32-bit interrupt vector for each interrupt, and defines the hardware

priority of exceptions. Each exception in the table is a 32-bit address that is loaded into the

program counter when that exception occurs. Exceptions 0 (stack pointer) through 15

(SysTick) are part of the standard ARM® Cortex-M3 NVIC, while exceptions 16 (Timer 1)

through 32 (Debug) are the peripheral interrupts specific to the STM32W108 peripherals.

Table 43.

NVIC exception table

Exception

Position

Description

-0

Stack top is loaded from first entry of vector table on reset.

Reset

Invoked on power up and warm reset. On first instruction, drops to

lowest priority (Thread mode). Asynchronous.

NMI

Cannot be stopped or preempted by any exception but reset.

Asynchronous.

Hard Fault

All classes of fault, when the fault cannot activate because of priority

or the Configurable Fault handler has been disabled. Synchronous.

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