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AM625 Datasheet(PDF) 13 Page - Texas Instruments |
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AM625 Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 255 page  6 Terminal Configuration and Functions 6.1 Pin Diagrams Note The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt is made to use "ball" only when referring to the physical package. Figure 6-1 shows the ball locations for the 425-ball flip chip ball grid array (FCCSP BGA) package to quickly locate signal names and ball grid numbering. This figure is used in conjunction with Section 6.2.1 through Table 6-74 (Pin Attributes table and all Signal Descriptions tables, including the Connectivity Requirements table). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A Not to scale VSS RSVD3 OLDI0 _CLK0P OLDI0 _CLK1N OLDI0_A5N OLDI0_A6N OLDI0_A7P VSS USB1_DP USB0 _RCALIB USB0_DM VSS CSI0_RXP2 CSI0_RXP1 CSI0 _RXCLKP VSS RGMII1_RX _CTL RGMII1 _TD2 RGMII1 _TXC RGMII1 _TD0 RGMII2 _TXC RGMII2 _RD3 RGMII2 _RD0 VSS VSS VSS MMC0_DAT6 OLDI0_A1N OLDI0 _CLK0N OLDI0 _CLK1P OLDI0_A5P OLDI0_A6P OLDI0_A7N VSS USB1_DM USB0_DP VSS CSI0_RXN2 CSI0_RXN1 CSI0 _RXCLKN VSS RGMII1 _RXC RGMII1 _TD3 RGMII1_TX _CTL RGMII1 _TD1 RGMII2 _TD2 RGMII2_RX _CTL RGMII2 _RXC MDIO0_MDC VSS MMC0_DAT5 MMC0_DAT7 OLDI0_A4P OLDI0_A4N USB1 _RCALIB USB0_VBUS CSI0_RXP3 CSI0_RXP0 RGMII1 _RD1 RGMII2 _TD3 RGMII2 _RD2 VOUT0 _PCLK VOUT0 _VSYNC MMC0_CLK MMC0_DAT4 OLDI0_A1P OLDI0_A3N VSS USB1_VBUS CSI0_RXN3 CSI0_RXN0 RGMII1 _RD2 RGMII1 _RD0 RGMII2 _RD1 MDIO0 _MDIO VOUT0 _HSYNC VOUT0 _DATA12 MMC0_DAT1 MMC0_DAT0 MMC0_DAT2 OLDI0_A0N OLDI0_A3P OLDI0_A2P VSS RSVD6 CSI0 _RXRCALIB RGMII1 _RD3 RGMII2 _TD1 RGMII2_TX _CTL VOUT0 _DATA15 VOUT0 _DATA11 VOUT0 _DATA13 VOUT0 _DATA7 DDR0_DQ14 VSS MMC0_CMD MMC0_DAT3 OLDI0_A0P OLDI0_A2N VDDA_1P8 _USB VDDA_3P3 _USB RSVD7 RGMII2 _TD0 VOUT0_DE VOUT0 _DATA14 VOUT0 _DATA6 VOUT0 _DATA5 VOUT0 _DATA4 DDR0_DQ15 DDR0_DQ12 DDR0_DM1 VSS VDDA_1P8 _OLDI0 VDDA_1P8 _OLDI0 VDDA_CORE _USB VDDA_CORE _CSIRX0 VDDA_1P8 _CSIRX0 VDDSHV2 CAP_VDDS2 VDDSHV2 VOUT0 _DATA9 VOUT0 _DATA3 VOUT0 _DATA2 DDR0_DQS1 DDR0_DQS1 _n DDR0_DQ11 DDR0_DQ13 VDD_CORE VSS VSS VSS VSS VDD_CORE VSS VDD_CORE VSS VOUT0 _DATA10 VOUT0 _DATA8 VOUT0 _DATA1 GPMC0 _WAIT1 DDR0_DQ8 DDR0_DQ10 DDR0_DQ9 RSVD5 CAP_VDDS4 VSS VDDA_PLL0 VDD_CORE VDDR_CORE VDDA_PLL1 VDDSHV3 VSS VOUT0 _DATA0 GPMC0 _WAIT0 GPMC0 _AD15 GPMC0 _AD14 DDR0_PAR RSVD4 DDR0_BG0 VDDSHV4 VSS VDDA _TEMP0 VDDR_CORE VSS VSS VSS VSS VSS VDDSHV3 GPMC0 _AD12 GPMC0 _AD13 GPMC0 _AD10 DDR0_A13 DDR0_A6 DDR0 _ALERT_n DDR0_A10 DDR0_A12 VDDS_DDR VDD_CORE VDDR_CORE VSS VDD_CORE VSS VSS VSS GPMC0 _AD11 GPMC0_AD7 GPMC0_AD8 GPMC0_AD9 DDR0_A8 DDR0_A7 DDR0_A9 DDR0_A11 VSS VDDS_DDR VSS VSS VDDR_CORE VDD_CORE VDDSHV3 CAP_VDDS3 GPMC0_AD6 GPMC0_AD5 GPMC0_AD4 GPMC0_CLK DDR0_BA1 DDR0_BG1 DDR0_WE_n DDR0_ACT _n VDD_CORE VDD_CORE VDDR_CORE VDD_CORE VDDR_CORE VSS VDDSHV3 GPMC0 _BE1n GPMC0_AD1 GPMC0_AD2 GPMC0_AD3 DDR0_BA0 DDR0_CAL0 DDR0_CAS _n DDR0_RAS _n VSS VSS VDDS_DDR _C VSS VSS VSS VDD_CORE VSS VSS VDDSHV1 GPMC0 _CSn0 GPMC0_DIR GPMC0 _BE0n_CLE GPMC0_AD0 DDR0_CK0 DDR0_CK0 _n DDR0_A3 DDR0_CS0 _n VDDS_DDR VDDA_MCU VDD_CORE VDDA_PLL2 VDD_CORE VDDSHV1 VSS GPMC0 _CSn1 GPMC0 _ADVn_ALE GPMC0_OEn _REn GPMC0_WEn DDR0_A5 DDR0_CS1 _n DDR0_A2 DDR0_A4 VSS VDDS_DDR VMON_3P3 _SOC VSS VSS VDDR_CORE VDD_CORE CAP_VDDS1 VSS GPMC0 _CSn2 GPMC0 _CSn3 GPMC0_WPn DDR0_A0 DDR0_A1 DDR0_ODT1 DDR0_CKE1 VSS VPP VDD_CORE VDDR_CORE VSS VDD_CORE VDDSHV6 CAP_VDDS6 OSPI0_D7 OSPI0_D4 OSPI0_DQS OSPI0_D5 DDR0_ODT0 DDR0_CKE0 DDR0_DM0 DDR0_DQ3 VDD_CORE VDDSHV _CANUART VMON_VSYS CAP_VDDS _MCU VSS CAP_VDDS0 VSS CAP_VDDS5 VSS VSS OSPI0 _CSn2 OSPI0_CLK OSPI0_D6 DDR0 _RESET0_n DDR0_DQ5 DDR0_DQ1 VDDS_OSC0 CAP_VDDS _CANUART VMON_1P8 _SOC VDDSHV _MCU VSS VDDSHV0 VDDA _TEMP1 VDDSHV5 VSS OSPI0 _CSn1 OSPI0_D1 OSPI0 _LBCLKO DDR0_DQ7 DDR0_DQ6 DDR0_DQ2 DDR0_DQ0 RSVD2 VDD _CANUART VDDSHV _MCU VSS VDDSHV0 USB1 _DRVVBUS RESET _REQz RESETSTA z OSPI0 _CSn0 OSPI0_D3 OSPI0_D2 DDR0_DQS0 DDR0_DQS0 _n DDR0_DQ4 MCU_MCAN1 _TX RSVD8 MCU_SPI0 _CS0 MCU _RESETz EMU0 UART0_TXD MCAN0_RX MCASP0 _AXR0 MCASP0 _AFSR PORz_OUT MMC2_DAT2 OSPI0 _CSn3 OSPI0_D0 MCU _ERRORn MCU_PORz MCU_MCAN1 _RX MCU_MCAN0 _TX MCU_SPI0 _D0 MCU_I2C0 _SDA TDO UART0_RXD EXTINTn MMC1_SDCD MCASP0 _AFSX MMC1_DAT3 MMC2_DAT3 MMC2_CLK WKUP _LFOSC0 _XO WKUP _LFOSC0 _XI WKUP _UART0 _TXD WKUP _UART0 _CTSn MCU_SPI0 _D1 EMU1 SPI0_CS1 MCAN0_TX MMC1_SDWP USB0 _DRVVBUS MMC1_DAT2 MMC2_CMD MMC2_DAT1 RSVD0 MCU_OSC0 _XI MCU_MCAN0 _RX WKUP _UART0 _RXD MCU_UART0 _RXD MCU_UART0 _RTSn PMIC_LPM _EN0 MCU_SPI0 _CS1 WKUP_I2C0 _SCL TRSTn TMS MCU_RESETS TATz SPI0_D0 SPI0_D1 UART0 _RTSn I2C0_SCL I2C1_SCL MCASP0 _AXR1 MCASP0 _AXR3 MCASP0 _ACLKX MMC1_DAT1 MMC1_CLK MMC2_SDWP MMC2_DAT0 VSS VSS RSVD1 MCU_OSC0 _XO WKUP _UART0 _RTSn MCU_UART0 _TXD MCU_UART0 _CTSn MCU_SPI0 _CLK MCU_I2C0 _SCL WKUP_I2C0 _SDA TCK TDI WKUP _CLKOUT0 SPI0_CS0 SPI0_CLK UART0 _CTSn I2C0_SDA I2C1_SDA EXT _REFCLK1 MCASP0 _AXR2 MCASP0 _ACLKR MMC1_CMD MMC1_DAT0 MMC2_SDCD VSS VSS Figure 6-1. ALW FCCSP Package (Bottom View) www.ti.com AM625, AM623 SPRSP58A – JUNE 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: AM625 AM623 |
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