AM625 datasheet(2/255 Pages) TI

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• Secure boot supported

– Hardware-enforced Root-of-Trust (RoT)

– Support to switch RoT via backup key

– Support for takeover protection, IP protection,

and anti-roll back protection

• Cryptographic acceleration supported

– Session-aware cryptographic engine with ability

to auto-switch key-material based on incoming

data stream

– Supports cryptographic cores

• AES – 128/192/256 Bits key sizes

• SHA2 – 224/256/384/512

• DRBG with true random number generator

• PKA (Public Key Accelerator) to Assist in

RSA/ECC processing

– DMA support

• Debugging security

– Secure software controlled debug access

– Security aware debugging

• Trusted Execution Environment (TEE) supported

– Arm TrustZone® based TEE

– Extensive firewall support for isolation

– Secure watchdog/timer/IPC

• Secure storage support

• On-the-Fly encryption support for OSPI interface in

XIP mode

PRU Subsystem:

• Dual-core Programmable Real-Time Unit

Subystem (PRUSS) running up to 333 MHz

• Intended for driving GPIO for cycle accurate

protocols such as additional:

– General Purpose Input/Output (GPIO)

– UARTs

– I2C

– External ADC

• 16KByte program memory per PRU with SECDED

ECC

• 8KB data memory per PRU with SECDED ECC

• 32KB general purpose memory with SECDED

ECC

• CRC32/16 HW accelerator

• Scratch PAD memory with 3 banks of 30 x 32-bit

registers

• 1 Industrial 64-bit timer with 9 capture and

16 compare events, along with slow and fast

compensation

• 1 interrupt controller (INTC), minimum of 64 input

events supported

High-Speed Interfaces:

• Integrated Ethernet switch supporting (total 2

external ports)

– RMII(10/100) or RGMII (10/100/1000)

– IEEE1588 (Annex D, Annex E, Annex F with

802.1AS PTP)

– Clause 45 MDIO PHY management

– Packet Classifier based on ALE engine with

512 classifiers

– Priority based flow control

– Time sensitive networking (TSN) support

– Four CPU H/W interrupt Pacing

– IP/UDP/TCP checksum offload in hardware

• Two USB2.0 Ports

– Port configurable as USB host, USB peripheral,

or USB Dual-Role Device (DRD mode)

– Integrated USB VBUS detection

– Trace over USB supported

General Connectivity:

• 9x Universal Asynchronous Receiver-Transmitters

(UART)

• 5x Serial Peripheral Interface (SPI) controllers

• 6x Inter-Integrated Circuit (I2C) ports

• 3x Multichannel Audio Serial Ports (McASP)

– Transmit and Receive Clocks up to 50 MHz

– Up to 16/10/6 Serial Data Pins across 3x

McASP with Independent TX and RX Clocks

– Supports Time Division Multiplexing (TDM),

Inter-IC Sound (I2S), and Similar Formats

– Supports Digital Audio Interface Transmission

(SPDIF, IEC60958-1, and AES-3 Formats)

– FIFO Buffers for Transmit and Receive (256

Bytes)

– Support for audio reference output clock

• 3x enhanced PWM modules (ePWM)

• 3x enhanced Quadrature Encoder Pulse modules

(eQEP)

• 3x enhanced Capture modules (eCAP)

• General-Purpose I/O (GPIO), All LVCMOS I/O can

be configured as GPIO

• 3x Controller Area Network (CAN) modules with

CAN-FD support

– Conforms w/ CAN Protocol 2.0 A, B and ISO

11898-1

– Full CAN FD support (up to 64 data bytes)

– Parity/ECC check for Message RAM

– Speed up to 8Mbps

AM625, AM623

SPRSP58A – JUNE 2022 – REVISED NOVEMBER 2022

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