AX88780 datasheet(12/49 Pages) ASIX

12 / 49 page

AX88780

3.0 Functional Description

3.1 Host Interface

AX88780 supports a very simple SRAM-like interface. There are only 3 control signals to operate the read or write.

For write operation, host activates CSN and WEN to low with address and data bus. AX88780 will decode and latched the

data into internal buffer. For normal operation, the WEN needs at least 3 clocks duration for one 32/16-bit write operation.

The CSN can always be driven, but WEN must at least be de-asserted 1 clock before next access. For read operation, host

asserts CSN and OEN at least 3 clocks to AX88780, the data will be valid after 3 clocks. For asynchronous access, please

add extra 3 clocks to read or write.

3.2 System Address Range

AX88780 is suitable to attach to SRAM controller, so it needs 64K memory space to operate. The designer can

allocate any block (64K) in system space. From offset 0000h to 7FFFh is for RX operation, and offset 8000h to F000h is

for TX operation. The internal configuration register of AX88780 is allocated in offset FC00h to FCFFh. Below is the

mapping of addressing.

R X ar ea

3276 8 b y t e s

XXXX _ 0000h

XXXX _8000 h

XXXX_ F C 0 0 h

T X ar ea

3174 4 b y t e s

R e g i s t er s ar ea

2 56 b y t e s

XXXX_ F D 0 0 h

N o u s e d ar ea

7 68 b y t e s

XXXX_ F F F F h

Figure 3 : 32-bit mode address mapping

3.3 TX Buffer Operation

AX88780 employs 4 descriptors to maintain transmit information, such as packet length, start bit. These descriptors

are located in offset FC20h, FC24h, FC28h and FC2Ch. Driver can choose any descriptor whenever there is data need to be

transmitted. Since there are only 4 descriptors, upon running out of descriptors, driver must wait for the descriptor is to be

released by AX88780.

3.4 RX Buffer Operation

AX88780 is built a 32K SRAM for RX operation. It utilizes ring structure to maintain the input data from PHY and

read out to host.

There are two pointer registers located in offset FC34h and FC38h. AX88780 will maintain

RXBOUND0 register. Upon it receives a valid packet from PHY it will update RXBOUND0 according to the packet length.

Driver reads data from AX88780 and maintains the RXBOUND1 register. When driver finishes reading packet, it must

update RXBOUND1 according to the packet length. AX88780 utilizes RXBOUND0 and RXBOUND1 to provide receive

buffer status, full or empty.

ASIX ELECTRONICS CORPORATION

AX88780 Datasheet(PDF) 12 Page - ASIX Electronics Corporation

AX88780 Datasheet(HTML) 12 Page - ASIX Electronics Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Datasheet Download

Link URL