AX88780 datasheet(27/49 Pages) ASIX

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AX88780

4.28 RXFILTER--RX Packet Filter Register

Offset Address = FC80h

Default = 32’h0000_002C

Field

Name

Type

Default

Description

31:6

All 0’s

Reserved

R/W

Reserved

MULTI_HASH

R/W

Receive Multicast packet by lookup hash table.

When this is enabled, AX88780 will receive multicast packet by the

hash mapping function. It will refer to HASTAB0, HASHTAB1,

HASHTAB2 and HASHTAB3 to look up the table.

1 = enable

0 = disable

BROADCAST

R/W

Receive Broadcast packet

When this bit is enabled, AX88780 will receive the broadcast packet

1 = enable

0 = disable

UNICAST

R/W

Receive Directed Packet.

If this bit is enabled, AX88780 will compare the destination address

field of received packet with the address of MAC (refer to MACID0,

MACID1, MACID2). When it is matched and good CRC, the packet

will be passed to driver. Otherwise it will be dropped.

1 = enable

0 = disable

MULTICAST

R/W

Receive all Multicast Packets.

If this bit is enabled, any multicast packet (good CRC) will be received

and passed to driver.

1 = enable

0 = disable

RXANY

R/W

Receive Anything.

If this bit is enabled, any packet whether it is good or fail will be

received and passed to driver.

1 = enable

0 = disable

4.29 MDIOCTRL--MDIO Control Register

Offset Address = FC84h

Default = 32’h0000_0000

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

WTEN

R/W

Write Enable.

Driver enables this bit to issue a write cycle to PHY, it will be cleared when

finished the write cycle

1 = enable

0 = disable

RDEN

R/W

Read Enable.

Driver enables this bit to issue a read cycle to PHY. This bit will be cleared

when finished the read cycle

1 = enable

0 = disable

12:8

PHYCRIDX R/W

5’b00000 PHY Register Index

If driver wants to access PHY, set this field to define the internal register

index of PHY.

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