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AX88780 Datasheet(PDF) 20 Page - ASIX Electronics Corporation

Part # AX88780
Description  High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller
PDF  49 Pages
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Manufacturer  ASIX [ASIX Electronics Corporation]
Direct Link  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX88780 Datasheet(HTML) 20 Page - ASIX Electronics Corporation

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AX88780
01: Descriptor 1 in transmitting
10: Descriptor 2 in transmitting
11: Descriptor 3 in transmitting
3
TXD3O
R/W
0
TX Descriptor3 Occupied
Driver set this bit to ‘1’ to indicate that it had used TX descriptor3. When the
transmission is finished, AX88780 will auto-clear this bit.
2
TXD2O
R/W
0
TX Descriptor2 Occupied
Driver set this bit to ‘1’ to indicate that it had used TX descriptor2. When the
transmission is finished, AX88780 will auto-clear this bit.
1
TXD1O
R/W
0
TX Descriptor1 Occupied
Driver set this bit to ‘1’ to indicate that it had used TX descriptor1. When the
transmission is finished, AX88780 will auto-clear this bit.
0
TXD0O
R/W
0
TX Descriptor0 Occupied
Driver set this bit to ‘1’ to indicate that it had used TX descriptor0. When the
transmission is finished, AX88780 will auto-clear this bit.
4.7 PHY_CTRL-- Internal PHY Control Register
Offset Address = FC1Ch
Default = 32’h0000_0000
Field
Name
Type
Default
Description
31:13
-
R
All 0’s
Reserved
12
SPD_GPIO1
R/W
0
Speed LED or GPIO1
When this bit is enabled, pin54 is as speed indicator, otherwise it is as
GPIO1 function and controlled by GPIO_CTRL register.
1= enable
0= disable
11
LNK_GPIO0
R/W
0
Link LED or GPIO0
When this bit is enabled, pin55 is as link/traffic indicator, otherwise it is
as GPIO0 function and controlled by GPIO_CTRL register.
1 = enable
0 = disable
10
FUL_EECS
R/W
0
EECS Pin as Full-Duplex LED
When this bit is enabled, EECS pin will be as full-duplex indicator and
EEDI pin will be as collision indicator.
1 = enable
0 = disable
9
PWDN
R/W
0
Power down PHY
When this bit is enabled, AX88780 will power down internal PHY.
1 = enable
0 = disable
8
PHY_EN
R/W
0
PHY Selection
When this bit is enabled, AX88780 will select internal PHY, otherwise it
will select external PHY.
1 = enable
0 = disable
7
-
R
0
Reserved
6:4
PHYOPMODE
R/W
3’b000
Internal 10/100M PHY operation mode
Driver can set these bits to control internal PHY operation mode.
3’b000 = auto-negotiation enable with all capability
3’b001 = auto-negotiation with 100BASE-TX FDX/HDX ability
3’b010 = auto-negotiation with 10BASE-T FDX/HDX ability
3’b011 = Reserved
3’b100 = Manual selection of 100BASE-TX FDX
3’b101 = Manual selection of 100BASE-TX HDX
3’b110 = Manual selection of 10BASE-T FDX
3’b111 = Manual selection of 10BASE-T HDX
20
ASIX ELECTRONICS CORPORATION



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