MCP3465R datasheet(40/110 Pages) MICROCHIP

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MCP3465R

DS20006414C-page 40

 2020-2021 Microchip Technology Inc.

5.3.1

ANALOG GAIN

The gain settings, from 0.33x to 16x, are done in the

analog domain. This analog gain is placed on each

ADC differential input. Each doubling of the gain

improves the thermal noise due to sampling by

approximately 3 dB, which means the lowest noise con-

figuration is obtained when using the highest analog

gain. The SNR, however, is degraded, since doubling

the gain factor reduces the maximum allowable input

signal amplitude by approximately 6 dB.

If the gain is set to 0.33x, the differential input range

theoretically becomes ±3 * VREF. However, the device

does not support input voltages outside of the power

supply voltage range. If large reference voltages are

used with this gain, the input voltage range will be

clipped between AGND and AVDD; therefore, the output

code span will be limited. This gain is useful when the

reference voltage is small and when the input signal

voltage is large.

The analog gain stage can be used to amplify very low

signals, but the differential input range of the

Delta-Sigma modulator must not be exceeded.

5.3.2

DIGITAL GAIN

When the gain setting is chosen from 16x to 64x, the

analog gain stays constant at 16x, and the additional

gain is done in the digital domain by a simple shift and

round of the output code. The digital gain range is

between 1x and 4x.

The output noise is approximately unchanged (except

for the quantization noise, which is slightly decreased).

The SNR is thus degraded by 6 dB per octave from 16x

to 64x settings.

This digital gain is useful for scaling up the signals with-

out using the host device (MCU) operations, but they

degrade the SNR and resolution (one bit per octave)

and do not significantly improve the noise performance,

except for very large OSR settings.

5.4

Delta-Sigma Modulator

5.4.1

ARCHITECTURE

The Delta-Sigma

 ADC includes a second-order

modulator with a multibit DAC architecture. Its 5-level

quantizer is a Flash ADC composed of four compara-

tors with equally spaced thresholds and a thermometer

output coding. The proprietary 5-level architecture

ensures minimum quantization noise at the outputs of

the modulators without disturbing the linearity or

inducing additional distortion.

Unlike most multibit DAC architectures, the 5-level

DAC used in this architecture is inherently linear; there-

fore, it does not degrade the ADC linearity and THD

performance. The sampling frequency is DMCLK;

therefore, the modulator outputs are refreshed at a

DMCLK rate. Figure 5-2 represents a simplified block

diagram of the Delta-Sigma modulator.

FIGURE 5-2:

Simplified Delta-Sigma ADC

Block Diagram.

5.4.2

MODULATOR OUTPUT BLOCK

The modulator output option enables users to apply

their own digital filtering on the output bit stream. By

setting EN_MDAT = 1 in the IRQ register, the modula-

tor output is available through the ADCDATA register

(0x0) with DMCLK rate. With this configuration, the

digital decimation filter is disabled in order to reduce

the current consumption and no data ready interrupt is

generated on any of the IRQ mechanisms.

Considering that the Delta-Sigma modulator has a

5-level output, given by the state of four comparators

with thermometer coding, the output is represented

using four bits, each bit representing the state of the cor-

responding comparator (see Table 5-4). The modulator

can be considered as a 5-level output at DMCLK rate.

When CLK_SEL[1:0] = 11 (internal oscillator with

external clock output), the AMCLK clock is present on

the SCK pin. This configuration allows a correct

synchronization of the bit stream when the internal

oscillator is used as the master clock source.

When CLK_SEL[1:0] = 00, the modulator outputs are

also synchronized with the SCK input, but the ratio

between MCLK and AMCLK must be taken into

account in the user applications to correctly retrieve the

desired bit stream.

TABLE 5-4:

DELTA-SIGMA MODULATOR

OUTPUT CODING

COMP[3:0]

Code

Modulator

Output Code

(Decimal)

MDAT

ADCDATA

Value

Equivalent

VREF

Voltage

1111

+VREF

0111

+VREF/2

0011

0001

-1

0001

-VREF/2

0000

-2

0000

-VREF

Differential Input

Voltage

(from Analog Mux)

Analog

nd Order

Loop

Filter

Output

Bitstream

Thermometer Coding

(to Digital Filter)

Delta-Sigma 2

nd Order 5-Level Modulator

Analog

Digital

5-Level DAC

Quantizer

5-Level Flash

ADC

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