MCP3465R datasheet(76/110 Pages) MICROCHIP

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MCP3465R

DS20006414C-page 76

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6.8

Interrupts Description

The MCP3465R device incorporates two interrupt

mechanisms to be able to synchronize the device with

an MCU and to warn against external perturbations.

There are three events that can generate interrupt flags:

• Data Ready

•POR

• CRC Error on the Register Map Configuration

A summary of the different mechanisms is available in

Table 6-3.

6.8.1

CONVERSION DATA READY (DR)

INTERRUPT

The data ready interrupt happens when a new

conversion is ready to be read on the ADCDATA register.

This event happens synchronously with DMCLK and at

each end of conversion. This interrupt is implemented

with two different and independent mechanisms:

STATUS byte on SDO and IRQ register Status bit.

STATUS byte on SDO. When the interrupt

occurs on the next STATUS byte transmitted on

SDO, the DR_STATUS bit will be logic low. Once

the STATUS byte has been transmitted, the

DR_STATUS bit appears as ‘1’ until a new

interrupt is present. If the interrupt occurs

between two STATUS byte transmissions, the

DR_STATUS bit on SDO will appear as equal to

‘0’ on the second reading.

IRQ register Status bit. When the interrupt

occurs, the DR_STATUS bit in the IRQ register

is set to ‘0’. Once the IRQ register has been fully

read, this DR_STATUS bit is reset to ‘1’. If the

interrupt occurs between two readings of the

IRQ register, the IRQ register Status bit appears

as equal to ‘0’ on the second reading.

6.8.2

POR INTERRUPT

The POR interrupt informs the user if a POR event has

happened.

This interrupt is implemented with two different and

independent mechanisms: STATUS byte on SDO and

IRQ register Status bit.

6.8.2.1

STATUS Byte on SDO

When the device has just powered up, on the first

STATUS byte transmitted on SDO (first communica-

tion), the POR_STATUS bit is logic low. Once the

STATUS byte has been transmitted, the POR_STATUS

bit appears as ‘1’ until the part is powered down. If a

POR event occurs between two STATUS byte trans-

missions, and if the part is properly repowered up, the

POR_STATUS bit on SDO will appear as equal to ‘0’ on

the latter reading. This mechanism can only work when

the power supplies are back above the POR thresholds

on the analog and digital cores, as retrieving data from

the SPI port is not possible when the device is in a POR

state.

6.8.2.2

IRQ Register Status Bit

When the device has just powered up, the

POR_STATUS bit in the IRQ register is set to ‘0’. Once

the

IRQ

has

been

fully

read,

this

POR_STATUS bit is once again reset to ‘1’. If a POR

event occurs between two readings of the IRQ register,

the IRQ register Status bit will appear as equal to ‘0’ on

the second reading. This mechanism can only work

when the power supplies are back above the POR

thresholds on the analog and digital cores.

TABLE 6-3:

INTERRUPT DESCRIPTION SUMMARY TABLE

Interrupt Flag Type

Description

Clearing Procedure

STATUS Byte

Three Status bits (DR_STATUS,

CRCCFG_STATUS, POR_STATUS) are

latched together after device address

detection and clocked out during each

command on the SDO STATUS byte.

Cleared when STATUS byte clocking is finished

(on the last SCK falling edge).

IRQ Register Status

Bits

IRQ register Status bits can be read when

reading the address 0x5 (IRQ register).

The IRQ latching occurs at the beginning

of the IRQ register reading.

Cleared when the IRQ register reading is

finished (on the last SCK falling edge).

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