MCP3465R datasheet(62/110 Pages) MICROCHIP

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MCP3465R

DS20006414C-page 62

 2020-2021 Microchip Technology Inc.

5.16.3

CAUSING DELAYED

RESET/RESTART

A third group of bits will generate a reset and a restart

that induce a new start-up delay (TADC_SETUP), so that

the internal analog operating points can be settled with

the new settings before the new conversion is started.

The reset is immediate; the start-up timer is only

restarted after a period of two MCLK periods (necessary

to handle the reset and to ensure that the restart is syn-

chronous with the master clock). Overall, the delay from

the reset to the actual restart of the conversion with the

new settings is then 2 MCLK + TADC_SETUP. This group

includes the CONFIG0 and RESERVED registers at

addresses, 0xB and 0xC. The CONFIG0 bits induce a

start-up timer delay only if they are changed to a new

value. If they are overwritten with the same value, they

will generate an immediate reset and restart. In Scan

mode, the reset and restart feature will just restart the

current conversion for this group of bits; the Scan cycle

is not modified and not restarted.

This third group of bits will induce a start-up timer delay,

even when ADC_MODE[1:0] = 10 or if the ADC is in

Standby mode.

During the reset and restart sequence, the reset is

immediate and resets the internal phases to the original

state, which can lead to a discontinuity in the clock out-

put frequency if the AMCLK clock output is enabled.

The restart is synchronous with the AMCLK generation

and is effective only after two MCLK periods.

Depending on the phase between the AMCLK and the

SPI commands, the 2-MCLK delay can turn into a

4-MCLK delay to ensure the proper synchronization of

the device. If very precise synchronization is required,

it is recommended to not change the register

configurations (i.e., not during conversions).

In MUX mode, the TIMER and SCAN registers do not

generate a reset and restart when written, except if the

SCAN register is modified to effectively enter in Scan

mode. In this case, the MUX mode is superseded by

the Scan mode immediately.

In Scan mode, a write access of the SCAN register,

during or between conversions within the Scan cycle,

will create a reset and restart of the whole Scan

sequence. Within the same conditions, a write access

on the TIMER register will not create a reset and restart

of the entire Scan sequence. However, during the

TTIMER_SCAN delay between Scan cycles, a write on

the SCAN register does not generate a reset and a

restart of the entire sequence. Within the same condi-

tions, a write on the TIMER register generates a reset

and a restart of the entire sequence.

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