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HC705V8GRS/D Datasheet(PDF) 124 Page - NXP Semiconductors |
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HC705V8GRS/D Datasheet(HTML) 124 Page - NXP Semiconductors |
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124 / 172 page ![]() SECTION 15: MESSAGE DATA LINK CONTROLLER Page 113 MC68HC705V8 Specification Rev. 2.1 15.4 MDLC PROTOCOL HANDLER The Protocol Handler is responsible for framing, collision detection, arbitration, CRC generation/checking, and error detection. The Protocol Handler conforms to SAE J1850 - Class B Data Communications Network Interface. 15.4.1 OUTLINE The Protocol Handler contains three main blocks: the State Machine, Rx Shift Register and Tx Shift Register, as shown below. Each block will now be described in more detail. Physical Interface To CPU Protocol Handler MUX Interface CPU Interface Rx/Tx Buffers To J1850 Bus MDLC Rx Shift Register Figure 15-8: MDLC Protocol Handler Outline To CPU Interface & Rx/Tx Buffers State Machine To MUX Interface 8 Tx Shift Register 8 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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