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DSP56307/D Datasheet(PDF) 27 Page - Motorola, Inc

Part # DSP56307/D
Description  24-BIT DIGITAL SIGNAL PROCESSOR
PDF  156 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

DSP56307/D Datasheet(HTML) 27 Page - Motorola, Inc

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Signals/Connections
Enhanced Synchronous Serial Interface 0
MOTOROLA
DSP56307 Technical Data
1-21
SC02
PC2
Input/
Output
Input or
Output
Input
Serial Control Signal 2
ÑSC02 is used for frame
sync I/O. SC02 is the frame sync for both the
transmitter and receiver in synchronous mode,
and for the transmitter only in asynchronous
mode. When configured as an output, this
signal is the internally generated frame sync
signal. When configured as an input, this signal
receives an external frame sync signal for the
transmitter (and the receiver in synchronous
operation).
Port C 2
ÑThe default configuration following
reset is GPIO input PC2. When configured as
PC2, signal direction is controlled through
PRR0. The signal can be configured as an ESSI
signal SC02 through PCR0.
Note:
This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
SCK0
PC3
Input/
Output
Input or
Output
Input
Serial Clock
ÑSCK0 is a bidirectional
Schmitt-trigger input signal providing the serial
bit rate clock for the ESSI. The SCK0 is a clock
input or output, used by both the transmitter
and receiver in synchronous modes or by the
transmitter in asynchronous modes.
Although an external serial clock can be
independent of and asynchronous to the DSP
system clock, it must exceed the minimum clock
cycle time of 6T (i.e., the system clock frequency
must be at least three times the external ESSI
clock frequency). The ESSI needs at least three
DSP phases inside each half of the serial clock.
Port C 3
ÑThe default configuration following
reset is GPIO input PC3. When configured as
PC3, signal direction is controlled through
PRR0. The signal can be configured as an ESSI
signal SCK0 through PCR0.
Note:
This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
Table 1-11
Enhanced Synchronous Serial Interface 0 (Continued)
Signal Name
Type
State During
Reset
Signal Description
Not Recommended for New Design



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