DSP56307SLASHD datasheet(63/156 Pages) MOTOROLA

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Specifications

External Memory Interface (Port A)

MOTOROLA

DSP56307 Technical Data

2-27

145 CAS assertion to WR

deassertion

tWCH

2.25

× T

C − 4.2

29.9

23.9

18.3

146 WR assertion pulse width

tWP

3.5

× T

C − 4.5

48.5

39.3

30.5

147 Last WR assertion to RAS

deassertion

tRWL

3.75

× T

C − 4.3

52.5

42.6

33.2

148 WR assertion to CAS

deassertion

tCWL

3.25

× T

C − 4.3

44.9

36.3

28.2

149 Data valid to CAS assertion

(write)

tDS

0.5

× T

C − 4.0

3.6

2.3

1.0

150 CAS assertion to data not

valid (write)

tDH

2.5

× T

C − 4.0

33.9

27.3

21.0

151 WR assertion to CAS assertion

tWCS

1.25

× T

C − 4.3

14.6

11.3

8.2

152 Last RD assertion to RAS

deassertion

tROH

3.5

× T

C − 4.0

49.0

39.8

31.0

153 RD assertion to data valid

tGA

66 MHz

2.5

× T

C − 7.5

80 MHz

2.5

× T

C − 6.5

100 MHz

2.5

× T

C − 5.7

30.4

24.8

19.3

154 RD deassertion to data not

valid6

tGZ

0.0

155 WR assertion to data active

0.75

× T

C − 0.3

11.1

9.1

7.2

156 WR deassertion to data high

impedance

0.25

× T

3.8

3.1

2.5

Notes:

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

The asynchronous delays specified in the expressions are valid for DSP56307

All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g.,

tPC equals 4 × TC for read-after-read or write-after-write sequences).

BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each

DRAM out-of page-access.

RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not

tGZ.

Table 2-11

DRAM Page Mode Timings, Three Wait States1, 2, 3, 4

No.

Characteristics

Symbol

Expression

66 MHz

80 MHz

100 MHz

Unit

Min Max Min Max Min Max

Not Recommended for New Design

DSP56307/D Datasheet(PDF) 63 Page - Motorola, Inc

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