DSP56307SLASHD datasheet(86/156 Pages) MOTOROLA

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DSP56307 Technical Data

MOTOROLA

Specifications

External Memory Interface (Port A)

Arbitration Timings

Table 2-18

Arbitration Bus Timings1

No.

Characteristics

Expression

100 MHz

Unit

Min Max

212 CLKOUT high to BR assertion/deassertion2

1.0

4.0

213 BG asserted/deasserted to CLKOUT high (setup)3

4.0

214 CLKOUT high to BG deasserted/asserted (hold)3

0.0

215 BB deassertion to CLKOUT high (input setup)3

4.0

216 CLKOUT high to BB assertion (input hold)3

0.0

217 CLKOUT high to BB assertion (output)

1.0

4.0

218 CLKOUT high to BB deassertion (output)

1.0

4.0

219 BB high to BB high impedance (output)

4.5

220 CLKOUT high to address and controls active

0.25

× T

2.5

221 CLKOUT high to address and controls high impedance

0.25

× T

2.5

222 CLKOUT high to AA active

0.25

× T

2.5

223 CLKOUT high to AA deassertion4

0.25

× T

C + 4.0

3.2

6.5

224 CLKOUT high to AA high impedance

0.75

× T

7.5

225 BG deassertion to BB assertion (output)5

2.5

× T

C + 5

226 BB (input) assertion to BG assertion5

× T

C + 5

Notes:

The asynchronous delays specified in the expressions are valid for DSP56307.

T212 is valid for address trace mode when the ATE bit (Bit 15) in the OMR is set. BR is

deasserted for internal accesses and asserted for external accesses.

T213, T214, T215, and T216 are valid only when the ABE bit (Bit 13) in the OMR is cleared.

When an expression appears with both a minimum and maximum value, use the expression

to calculate worst case.

Asynchronous bus arbitration mode inserts a delay between changes in BG and BB until the

change is actually ÒseenÓ by the chip internally (i.e., this delay is required because internal

chip operation is synchronous). T225 and T226 are valid for asynchronous bus arbitration

mode only (i.e., when the ABE bit in the OMR is set). If ABE is set, T213, T214, T215, and T216

are not required for proper operation, and BG and BB do not have setup and input hold

requirements with respect to CLKOUT. The delay between the deassertion of BG for a

DSP56307 and the assertion of a second BG to another DSP56307 must be greater than the

sum of T225 (for the first chip) and T226 (for the second chip) to prevent bus access by more

than one DSP at a time.

Not Recommended for New Design

DSP56307/D Datasheet(PDF) 86 Page - Motorola, Inc

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