STM32U535NET6QTR datasheet(48/278 Pages) STMICROELECTRONICS

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Functional overview

STM32U535xx

48/278

DS14217 Rev 1

3.11.1

RCC TrustZone security

When the TrustZone security is activated by the TZEN option bit, the RCC is switched in

TrustZone security mode.

The RCC TrustZone security secures some RCC system configuration and peripheral

configuration clock from being read or modified by nonsecure accesses: when a peripheral

is secure, the related peripheral clock, reset, clock source selection and clock enable during

low-power modes control bits are secure.

A peripheral is in secure state:

•

when its corresponding SEC security bit is set in the TZSC (TrustZone security

controller), for securable peripherals.

•

when a security feature of this peripheral is enabled through its dedicated bits, for

TrustZone-aware peripherals.

3.12

Clock recovery system (CRS)

The devices embed a special block that allows automatic trimming of the internal 48 MHz

oscillator to guarantee its optimal accuracy over the whole device operational range. This

automatic trimming is based on the external synchronization signal, that is either derived

from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin

or generated by user software. For faster lock-in during startup, automatic trimming and

manual trimming action can be combined.

3.13

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain),

as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions.

After reset, all GPIOs are in analog mode to reduce power consumption.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

3.13.1

GPIOs TrustZone security

Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O

pin is configured as secure, its corresponding configuration bits for alternate function, mode

selection, I/O data are secure against a nonsecure access. The associated registers bit

access is restricted to a secure software only. After reset, all GPIO ports are secure.

3.14

Low-power general-purpose inputs/outputs (LPGPIO)

The LPGPIO allows dynamic I/O control in Stop 2 mode thanks to LPDMA1. Up to 16 I/Os

can be configured and controlled as input or output (open-drain or push-pull depending on

GPIO configuration).

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