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STM32U535NET6QTR Datasheet(PDF) 253 Page - STMicroelectronics |
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STM32U535NET6QTR Datasheet(HTML) 253 Page - STMicroelectronics |
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253 / 278 page ![]() DS14217 Rev 1 253/278 STM32U535xx Electrical characteristics 253 Figure 58. JTAG timing diagram Figure 59. SWD timing diagram tisu(SWDIO) SWDIO input setup time - 1 - - ns tih(SWDIO) SWDIO input hold time - 2.5 - - tov(SWDIO) SWDIO output valid time 2.7 V ≤ VDD ≤ 3.6 V - 10.5 15 1.71 V ≤ VDD ≤ 3.6 V - 10.5 23 toh(SWDIO) SWDIO output hold time - 7.5 - - 1. Evaluated by characterization. Not tested in production. Table 131. SWD characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit MSv40458V1 TDI/TMS TCK TDO tc(TCK) tw(TCKL) t w(TCKH) th(TMS/TDI) tsu(TMS/TDI) tov(TDO) toh(TDO) MSv40459V1 SWDIO SWCLK SWDIO tc(SWCLK) twSWCLKL) tw(SWCLKH) th(SWDIO) tsu(SWDIO) tov(SWDIO) toh(SWDIO) (receive) (transmit) |
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