84329B DATA SHEET

REVISION B 07/29/14

4

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL

FREQUENCY SYNTHESIZER

Function Tables

Table 3A. Parallel and Serial Mode Function Table

NOTE:

L = LOW

H = HIGH

X = Don’t care

 = Rising edge transition

 = Falling edge transition

Table 3B. Programmable VCO Frequency Function Table

NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.

Table 3C. Programmable Output DividerFunction Table

Inputs

Conditions

nP_LOAD

M

N

S_LOAD

S_CLOCK

S_DATA

X

X

X

X

X

X

Reset. M and N bits are all set HIGH.

L

Data

Data

X

X

X

Data on M and N inputs passed directly to the M divider and

N output divider. TEST mode 000.



Data

Data

L

X

X

Data is latched into input registers and remains loaded until

next LOW transition or until a serial event occurs.

HX

X

L



Data

Serial input mode. Shift register is loaded with data on S_DATA

on each rising edge of S_CLOCK.

HX

X



L

Data

Contents of the shift register are passed to the M divider and

N output divider.

HX

X



L

Data

M divider and N output divider values are latched.

H

X

X

L

X

X

Parallel or serial input do not affect shift registers.

VCO Frequency

(MHz)

M Divide

256

128

64

32

16

8421

M8

M7

M6

M5

M4

M3

M2

M1

M0

250

250

011111010

251

251

011111011

252

252

011111100

253

253

011111101

•

•

•••••••••

•

•

•••••••••

509

509

111111101

510

510

111111110

511

511

111111111

Inputs

N Divider Value

Output Frequency (MHz)

N1

N0

Minimum

Maximum

0

0

1

250

700

0

1

2

125

350

1

0

4

62.5

175

1

1

8

31.25

87.5