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DSP56321RM/D Datasheet(PDF) 22 Page - NXP Semiconductors

Part # DSP56321RM/D
Description  24-Bit Digital Signal Processor
PDF  88 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

DSP56321RM/D Datasheet(HTML) 22 Page - NXP Semiconductors

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1-16
Timers
1.11 Timers
The DSP56321T has three identical and independent timers. Each timer can use internal or external
clocking and can either interrupt the DSP56321T after a specified number of events (clocks) or signal an
external device after counting a specific number of internal events.
Table 1-14. Triple Timer Signals
Signal Name
Type
State During
Reset1,2
Signal Description
TIO0
Input or Output Ignored Input
Timer 0 Schmitt-Trigger Input/Output— When Timer 0 functions
as an external event counter or in measurement mode, TIO0 is
used as input. When Timer 0 functions in watchdog, timer, or pulse
modulation mode, TIO0 is used as output.
The default mode after reset is GPIO input. TIO0 can be changed
to output or configured as a timer I/O through the Timer 0
Control/Status Register (TCSR0).
TIO1
Input or Output Ignored Input
Timer 1 Schmitt-Trigger Input/Output— When Timer 1 functions
as an external event counter or in measurement mode, TIO1 is
used as input. When Timer 1 functions in watchdog, timer, or pulse
modulation mode, TIO1 is used as output.
The default mode after reset is GPIO input. TIO1 can be changed
to output or configured as a timer I/O through the Timer 1
Control/Status Register (TCSR1).
TIO2
Input or Output Ignored Input
Timer 2 Schmitt-Trigger Input/Output— When Timer 2 functions
as an external event counter or in measurement mode, TIO2 is
used as input. When Timer 2 functions in watchdog, timer, or pulse
modulation mode, TIO2 is used as output.
The default mode after reset is GPIO input. TIO2 can be changed
to output or configured as a timer I/O through the Timer 2
Control/Status Register (TCSR2).
Notes:
1.
In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines maintain the last output state even if the drivers are tri-stated,
because they have internal weak keeper circuits.
2.
The Wait processing state does not affect the signal state.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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