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DSP56321RM/D Datasheet(PDF) 32 Page - NXP Semiconductors

Part # DSP56321RM/D
Description  24-Bit Digital Signal Processor
PDF  88 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

DSP56321RM/D Datasheet(HTML) 32 Page - NXP Semiconductors

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2-8
AC Electrical Characteristics
25
Delay from IRQA assertion to fetch of first
instruction (when exiting Stop)2, 3
DPLL is not active during Stop (PCTL Bit 1 =
0) and Stop delay is enabled (Operating Mode
Register Bit 6 = 0)
DPLL is not active during Stop (PCTL Bit 1 =
0) and Stop delay is not enabled (Operating
Mode Register Bit 6 = 1)
DPLL is active during Stop (PCTL Bit 1 = 1;
Implies No Stop Delay)
DPLT + (128K
× T
C)
DPLT + (23.75 ± 0.5)
× T
C
(8.25
± 0.5) × T
C
589.2
6.9
35.3
732.4
150.1
39.6
540.6
6.9
32.3
683.8
150.1
35.5
µs
µs
ns
26
Duration of level sensitive IRQA assertion
to ensure interrupt service (when exiting
Stop)2, 3
DPLL is not active during Stop (PCTL bit 1 =
0) and Stop delay is enabled (Operating Mode
Register Bit 6 = 0)
DPLL is not active during Stop (PCTL bit 1 =
0) and Stop delay is not enabled (Operating
Mode Register Bit 6 = 1)
DPLL is active during Stop ((PCTL bit 1 = 0;
implies no Stop delay)
DPLT + (128 K
× T
C)
DPLT + (20.5
± 0.5) × T
C
5.5
× T
C
589.2
6.9
25.0
—
—
—
540.6
6.9
22.9
—
—
—
µs
µs
ns
27
Interrupt Requests Rate
HI08, ESSI, SCI, Timer
DMA
IRQ, NMI (edge trigger)
IRQ, NMI (level trigger)
12TC
8TC
8TC
12TC
—
—
—
—
54.6
36.4
36.4
54.6
—
—
—
—
50.0
33.4
33.4
50.0
ns
ns
ns
ns
28
DMA Requests Rate
Data read from HI08, ESSI, SCI
Data write to HI08, ESSI, SCI
Timer
IRQ, NMI (edge trigger)
6TC
7TC
2TC
3TC
—
—
—
—
27.3
31.9
9.1
13.7
—
—
—
—
25.0
29.2
8.3
12.5
ns
ns
ns
ns
29
Delay from IRQA, IRQB, IRQC, IRQD, NMI
assertion to external memory (DMA source)
access address out valid
4.25
× T
C + 2.0
21.34
—
19.72
—
ns
Notes:
1.
When fast interrupts are used and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19
through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted
Edge-triggered mode is recommended when fast interrupts are used. Long interrupts are recommended for
Level-sensitive mode.
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued)
No.
Characteristics
Expression
220 MHz
240 MHz
Unit
Min
Max
Min
Max
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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