DSP56321RMSLASHD datasheet(7/88 Pages) NXP

7 / 88 page

1-1

Chapter 1

Signal/

Connection

Descriptions

1.1 Signal Groupings

The DSP56321T input and output signals are organized into functional groups as shown in Table 1-1.

Figure 1-1 diagrams the DSP56321T signals by functional group. The remainder of this chapter

describes the signal pins in each functional group.

Note:

This chapter refers to a number of configuration registers used to select individual multiplexed

signal functionality. Refer to the DSP56321 Reference Manual (DSP56321RM/D) for details on

these configuration registers.

Table 1-1. DSP56321T Functional Signal Groupings

Functional Group

Number

Signals

Power (VCC)

Ground (GND)

Clock

PLL

Address bus

Port A1

Data bus

Bus control

Interrupt and mode control

Host interface (HI08)

Port B2

Enhanced synchronous serial interface (ESSI)

Ports C and D3

Serial communication interface (SCI)

Port E4

Timer

OnCE/JTAG Port

Notes:

Port A signals define the external memory interface port, including the external address bus, data

bus, and control signals.

Port B signals are the HI08 port signals multiplexed with the GPIO signals.

Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.

Port E signals are the SCI port signals multiplexed with the GPIO signals.

There are 8 signal lines that are not connected internally. These are designated no connect (NC) in

the package description (see Chapter 3). There are also two lines that are reserved.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56321RM/D Datasheet(PDF) 7 Page - NXP Semiconductors

DSP56321RM/D Datasheet(HTML) 7 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datasheet Download

Link URL