DSP56321RMSLASHD datasheet(10/88 Pages) NXP

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1-4

External Memory Expansion Port (Port A)

1.5 External Memory Expansion Port (Port A)

Note:

When the DSP56321T enters a low-power standby mode (stop or wait), it releases bus

mastership and tri-states the relevant Port A signals: A[0–17], D[0–23], AA0/RAS0–AA3/RAS3,

, WR, BB, CAS.

1.5.1 External Address Bus

1.5.2 External Data Bus

Table 1-5. External Address Bus Signals

Signal

Name

Type

State During

Reset, Stop, or

Wait

Signal Description

A[0–17]

Output

Tri-stated

Address Bus—When the DSP is the bus master, A[0–17] are

active-high outputs that specify the address for external

program and data memory accesses. Otherwise, the signals

are tri-stated. To minimize power dissipation, A[0–17] do not

change state when external memory spaces are not being

accessed.

Table 1-6. External Data Bus Signals

Signal

Name

Type

State

During

Reset

State

During

Stop or

Wait

Signal Description

D[0–23]

Input/ Output

Ignored

Input

Last state:

Input:

Ignored

Output:

Last value

Data Bus—When the DSP is the bus master, D[0–23] are

active-high, bidirectional input/outputs that provide the

bidirectional data bus for external program and data memory

accesses. Otherwise, D[0–23] drivers are tri-stated. If the last

state is output, these lines maintain the last output state even if

all drivers are tri-stated, because they have internal weak

keeper circuits.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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