M66596FP datasheet(96/133 Pages) RENESAS

96 / 133 page

M66596FP/WG

rev .1.00

2006.3.14

page 94 of 127

3.9.3.2 Counter initialization in the Peripheral mode

The controller initializes the interval counter under the following conditions.

(1) H/W reset

The IITV bit is initialized.

(2) S/W reset by USBE bit

The IITV bit is initialized.

(3) The return from Low-power sleep state

The IITV bit is initialized.

(4) Buffer memory initialization by the ACLRM bit.

A count is initialized although an IITV bit is not initialized. By setting an ACLRM bit to 0, the setting value of

IITV

is counted from the beginning.

After the interval counter has been initialized, the counter is started under the following conditions, when a

packet has been transferred normally.

(1)

An SOF is received following transmission of data in response to an IN token, in the “PID-BUF” state

(2)

An SOF is received after data following an OUT token is received in the “PID=BUF” state

The interval counter is not initialized under the conditions noted below.

(1)

The pipe is disabled

The “PID=NAK or STALL” setting temporarily stops the count, and the count resumes upon “PID=BUF”.

(2)

The USB is suspended and Bus reset

The count stops temporarily and then continues when SOF packet is received.

M66596FP Datasheet(PDF) 96 Page - Renesas Technology Corp