ZSPM2000 Datasheet

© 2016 Integrated Device Technology, Inc.

16

January 27, 2016

3

Functional Description

3.1.

Power Supply Circuitry, Reference Decoupling, and Grounding

The ZSPM2000 incorporates several internal power regulators in order to derive all required supply and bias

voltages from a single external 5 V supply voltage on the VDD50DRV and VDD50 pins. The integrated MOSFET

driver supply terminal VDD50DRV must be decoupled to the PGND pin (1.0µF minimum; 4.7µF recommended).

Recommendation: Add a 10

Ω resistor between the VDD50DRV and VDD50 pins to provide sufficient decoupling

between the pins.

Decoupling capacitors are required at the VDD50, VDD33, VDD18, and AVDD18 pins (1.0µF minimum; 4.7µF

recommended). A small load current can be drawn from the VDD33 pin. For example, this can be used to supply

pull-up resistors.

The reference voltages required for the analog-to-digital converters (ADCs) are generated within the ZSPM2000.

External decoupling must be provided between the VREFP and ADCVREF pins. Therefore, a 4.7µF capacitor is

required at the VREFP pin and a 100nF capacitor at ADCVREF pin. The two pins should be connected with

approximately 50

Ω resistance in order to provide sufficient decoupling between the pins.

Three different ground connections are available on the outside of the package. Recommendation: Tie the AGND

and the PAD together while separating the ground loop for the driver ground (PGND). Also use a single tie point

close to the ZSPM2000 to tie the two ground connections together.

3.2.

Reset/Start-up Behavior

The ZSPM2000 employs an internal power-on-reset (POR) circuit to ensure proper start up and shut down with a

changing supply voltage. Once the supply voltage increases above the POR threshold voltage, the ZSPM2000

begins the internal start-up process. Upon its completion, the device is ready for operation.

3.3.

Digital Power Control

3.3.1.

Overview

The digital power control loop consists of the integral parts required for the control functionality of the ZSPM2000.

A high-speed analog front-end is used to digitize the output voltage. A digital control core uses the acquired

information to provide duty-cycle information to the PWM, which controls the drive signals to the power stage.

3.3.2.

Switching Frequency

The ZSPM2000 supports the switching frequencies listed in Table 3.1.

Table 3.1

Supported Switching Frequencies

Supported Switching Frequencies

1000kHz

571.4kHz

400.0kHz

266.6kHz

800kHz

500.0kHz

333.3kHz

222.0kHz

666.6kHz

444.4kHz

285.7kHz

177.0kHz