ZSPM2000 Datasheet

© 2016 Integrated Device Technology, Inc.

17

January 27, 2016

3.3.3.

Output Voltage Feedback

The voltage feedback signal is sampled with a high-speed analog front-end. The feedback voltage is differentially

measured and subtracted from the voltage reference provided by a reference digital-to-analog converter (DAC)

using an error amplifier. A flash ADC is then used to convert the voltage into its digital equivalent. This is followed

by internal digital filtering to improve the system’s noise rejection.

Although the reference DAC generates a voltage up to 1.44V, keeping the voltage on the feedback pin (VFBP) at

approximately 1.20V is recommended to guarantee sufficient headroom. If a larger output voltage is required, an

external feedback divider is required.

3.3.4.

Digital Compensator

The sampled output voltage is processed by a digital control loop in order to modulate the DPWM output signals

controlling the power stage. This digital control loop works as a voltage-mode controller using a PID-type

compensation. The basic structure of the controller is shown in Figure 3.1. The proprietary State-Law™ Control

(SLC) concept features two parallel compensators for steady-state operation and fast transient operation. The

coefficients for the two modes can be derived using the Pink Power Designer™ graphical user interface (GUI).

The ZSPM2000 implements fast, reliable switching between the different compensation modes in order to ensure

good transient performance and a quiet steady state. This allows tuning the compensators individually for the

respective needs; i.e., quiet steady-state and fast transient performance.

Figure 3.1

Simplified Block Diagram of the Digital Compensation

Additionally, three different techniques are used to improve transient performance further. Tru-sample

Technology™ is used to acquire fast, accurate, and continuous information about the output voltage so that the

ZSPM2000 can react quickly to any change in output voltage. Tru-sample Technology™ reduces phase-lag

caused by sampling delays, reduces noise sensitivity, and improves transient performance.

The Sub-cycle Response™ (SCR) technique, a method to drive the DPWM asynchronously during load

transients, allows limiting the maximum deviation of the output voltage and allows recharging the output

capacitors faster.

A non-linear gain adjustment is used during large load transients to boost the loop gain and reduce the settling

time.

Digital PID

Compensator

Steady-state

Transient

Coefficients

Non-linear

Gain

Operation

Mode

Detection

Digital Error Signal

Duty Cycle