AMD-766AC datasheet(52/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

C1A40: EIDE Controller Configuration Register

Configuration space; function 1; offset: 43-40h. Default: 0000 0400h.

31:24

23:20

19:16

15:0

Reserved

CABLE

IDE_CONFIG

IDE_CONFIG[0] Secondary Channel Enable, SECEN. Read-write. 1=The secondary port of the EIDE controller

is enabled.

IDE_CONFIG[1] Primary Channel Enable, PRIEN. Read-write. 1=The primary port of the EIDE controller is

enabled.

IDE_CONFIG[4:2] MBLD. Must be left in their default state. Read-write. These bits are required to be left in their

default state; otherwise undefined behavior will result.

IDE_CONFIG[7:5] Reserved.

IDE_CONFIG[11:8] MBLD. Must be left in their default state. Read-write. These bits are required to be left in

their default state; otherwise undefined behavior will result.

IDE CONFIG[12] Secondary Posted Write Buffer, SECPWB. Read-write. 1=Enable the EIDE secondary port

PIO-mode posted-write buffer. Only 32-bit writes to the data port are allowed when this bit is set.

IDE CONFIG[13] Secondary Read Prefetch Buffer, SECRPB. Read-write. 1=Enable the EIDE secondary port

read-prefetch buffer.

IDE CONFIG[14] Primary Posted Write Buffer, PRIPWB. Read-write. 1=Enable the EIDE primary port PIO-

mode posted-write buffer. Only 32-bit writes to the data port are allowed when this bit is set.

IDE CONFIG[15] Primary Read Prefetch Buffer, PRIRPB. Read-write. 1=Enable the EIDE primary port read-

prefetch buffer.

CABLE. Read-write. These bits are expected to be programmed by BIOS to specify the cable type of each of the

IDE drives to the driver. 1=High speed 80-pin cable is present. The bits specify the drive as follows:

•

Bit[16]: primary master.

•

Bit[17]: primary slave.

•

Bit[18]: secondary master.

•

Bit[19]: secondary slave.

RW. Read-write. These bits are read-write accessible through software; they control no hardware.

C1A48: EIDE Controller Drive Timing Control

Configuration space; function 1; offset: 4B-48h. Default: A8A8 A8A8h. Read-write.

This register specifies timing for PIO data transfers (not 171h though 177h or 1F1h though 1F7h) and multi-word

DMA transfers. The value in each 4-bit field, plus one, specifies a time period in 30 nanosecond PCI clocks. Note:

The default state, A8h, results in a recovery time of 270ns and an active pulse width of 330ns for a 30ns PCI clock

(total cycle time = 600ns) which corresponds to ATA PIO Mode 0.

Note: PIO modes are controlled via C1A48 and C1A4C. To set the timing associated with the various modes,

C1A4C should be left at its default value and the appropriate byte of C1A48 should be programmed as follows: mode

0=A8h; mode 1=65h; mode 2=42h; mode 3=22h; mode 4=20h.

31:28

27:24

23:20

19:16

15:12

11:8

7:4

3:0

PD0PW

PD0RT

PD1PW

PD1RT

SD0PW

SD0RT

SD1PW

SD1RT

SD1RT[3:0] Secondary Drive 1 Minimum Recovery Time.

SD1PW[3:0] Secondary Drive 1 Active Pulse Width.

SD0RT[3:0] Secondary Drive 0 Minimum Recovery Time.

SD0PW[3:0] Secondary Drive 0 Active Pulse Width.

PD1RT[3:0] Primary Drive 1 Minimum Recovery Time.

PD1PW[3:0] Primary Drive 1 Active Pulse Width.

PD0RT[3:0] Primary Drive 0 Minimum Recovery Time.

PD0PW[3:0] Primary Drive 0 Active Pulse Width.

AMD-766AC Datasheet(PDF) 52 Page - Advanced Micro Devices

AMD-766AC Datasheet(HTML) 52 Page - Advanced Micro Devices

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