LTP8800-1AIPVPBF datasheet(9/20 Pages) AD

9 / 20 page

LTP8800-1A

Rev. B

For more information www.analog.com

APPLICATIONS INFORMATION

PolyPhase CONFIGURATION

When configuring a PolyPhase® rail with multiple

LTP8800-1A, the user must share the SYNC and ISHARE

pins. An external clock source at the desired switching

frequency is required for current sharing applications. The

internal digital phase-locked loop is capable of determine

the frequency on the SYNC pin and locking the internal

switching frequency to the external frequency. The lock

or capture range is ±10% of the switching frequency

(Register 0x33). The relative phasing of all the channels

should be spaced equally. This can be configured using

be added.

PolyPhase LOAD SHARING

Multiple LTP8800-1A can be arrayed in order to provide a

balanced load-share solution by bussing the ISHARE pins.

Figure 4 illustrates a 2-phase design sharing connections

required for load sharing.

PMBus COMMANDS AND LTPOWERPLAY

PMBus Commands

There are multiple PMBus commands and manufacturer

specific commands, which can be customized to adjust

the settings of LTP8800-1A μModule, as listed in Table 1.

These commands comply to the PMBus Power System

Management Protocol. Users are encouraged to refer to

the PMBus Communication and Command Processing

section for details.

VIN

SYNC

CTRL

SMBALERT

SDA

SCL

ISHARE

VS–

VS+

VOUT

4.7µF

LTP8800-1A

7V0

3V3

VIN

45V TO 65V

3V3

2.00k

100pF

100µF

×16

560µF

×16

PMBus

ISHARE BUS

1MHz CLK

VIN

SYNC

CTRL

SMBALERT

SDA

SCL

ISHARE

VS+

VOUT

4.7µF

LTP8800-1A

88001a F04

7V0

3V3

VIN

45V TO 65V

3V3

PMBus

ISHARE BUS

1MHz CLK

210Ω

ADD

750Ω

ADD

GND

1.00k

7.5Ω

VS–

2.00k

100pF

1.00k

7.5Ω

VOUT 0.75V 300A

Figure 4. 2-Phase Operation Producing 0.75V at 300A

LTP8800-1AIPVPBF Datasheet(PDF) 9 Page - Analog Devices

LTP8800-1AIPVPBF Datasheet(HTML) 9 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL