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JS28F320J3F75 Datasheet(PDF) 29 Page - Numonyx B.V

Part # JS28F320J3F75
Description  Numonyx® Embedded Flash Memory (J3 65nm) Single Bit per Cell (SBC)
PDF  67 Pages
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

JS28F320J3F75 Datasheet(HTML) 29 Page - Numonyx B.V

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Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Datasheet
28
7.2
Program, Erase, Block-Lock Specifications
7.3
Reset Specifications
Note:
STS is shown in its default mode (RY/BY#).
Table 13: Configuration Performance
#
Symbol
Parameter
Typ
Max
Unit
Notes
W200
tPROG/W
Program Time
Single word
40
175
µs
1,2,3,4,6
W250
tPROG
Buffer Program Time
Aligned 16 Words BP Time (32 Bytes)
128
654
µs
1,2,3,4,5,6
Aligned 128 Words BP Time (256 Bytes)
400
2000
µs
1,2,3,4,5,6
Aligned 256 Words BP Time
720
3600
µs
1,2,3,4,5,6
W501
tERS/AB
Block Erase Time
1.0
4.0
sec
1,2,3,4,6
W650
tlks
Set Lock-Bit Time
50
60
µs
1,2,3,4,6
W651
tlkc
Clear Block Lock-Bits Time
0.5
1
sec
1,2,3,4,6
W600
tSUSP/P
Program Suspend Latency Time to Read
15
20
µs
1,2,3,6
W601
tSUSP/E
Erase Suspend Latency Time to Read
15
20
µs
1,2,3,6
W602
tERS/SUSP Erase to Suspend
500
—
µs
1,7
W652
tSTS
STS Pulse Width Low Time
500
—
ns
1
W702
tBC/MB
blank check
Array Block
3.2
—
ms
—
Notes:
1.
Typical values measured at TA = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to
change based on device characterization.
2.
These performance numbers are valid for all speed versions.
3.
Sampled but not 100% tested.
4.
Excludes system-level overhead.
5.
These values are valid when the buffer is full, and the start address is aligned.
6.
Max values are measured at worst case temperature, data pattern and VCC corner within 100K cycles. But for W650, W651,
W600 and W601, the Max value are expressed at +25 °C or -40 °C.
7.
W602 is the typical time between an initial block erase or erase resume command and then a subsequent erase suspend
command. Violating the specification repeatedly during any particular block erase may cause erase failures.
Figure 12: AC Waveform for Reset Operation
P3
P1
P2
P1
STS (R)
RP# (P)
Vcc



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