JS28F320J3F75 datasheet(25/67 Pages) NUMONYX

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Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Datasheet

7.1

Read Specifications

Notes:

CEX low is defined as the combination of pins CE0, CE1 and CE2 that enable the device. CEX high is defined as the

combination of pins CE0, CE1, and CE2 that disable the device (see

Table 17, “Chip Enable Truth Table for 32-

, 64-, 128-Mb” on page 30).

See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.

OE# may be delayed up to tELQV-tGLQV after the falling edge of CEX (see note 1 and Table 17, “Chip Enable Truth

Table for 32-, 64-, 128-Mb” on page 30) without impact on tELQV.

See

Figure 13, “AC Input/Output Reference Waveform” on page 29 and Figure 14, “Transient

Equivalent Testing Load Circuit” on page 29 for testing characteristics.

Sampled, not 100% tested.

For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).

Table 11: Read Operations

Asynchronous Specifications VCC = 2.7 V–3.6 V (3) and VCCQ = 2.7 V–3.6 V(3)

Sym

Parameter

Density

Min

Max

Unit

Notes

tAVAV

Read/Write Cycle Time

All

—

1,2

tAVQV

Address to Output Delay

—

1,2

tELQV

CEX to Output Delay

—

1,2

tGLQV

OE# to Non-Array Output Delay

—

1,2,4

tPHQV

RP# High to Output Delay

32 Mbit

—

150

1,2

64 Mbit

—

180

1,2

128 Mbit

—

210

1,2

tELQX

CEX to Output in Low Z

All

—

1,2,5

tGLQX

OE# to Output in Low Z

—

1,2,5

tEHQZ

CEX High to Output in High Z

—

1,2,5

tGHQZ

OE# High to Output in High Z

—

1,2,5

R10

tOH

Output Hold from Address, CEX, or OE#

Change, Whichever Occurs First

—

1,2,5

R11

tELFL/tELFH

CEX Low to BYTE# High or Low

—

1,2,5

R12

tFLQV/tFHQV BYTE# to Output Delay

—

µs

1,2

R13

tFLQZ

BYTE# to Output in High Z

—

µs

1,2,5

R14

tEHEL

CEx High to CEx Low

—

1,2,5

R15

tAPA

Page Address Access Time

—

5, 6

R16

tGLQV

OE# to Array Output Delay

—

1,2,4

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