 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TSI721 Datasheet(PDF) 19 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
TSI721 Datasheet(HTML) 19 Page - Renesas Technology Corp |
|
|
19 / 67 page  Tsi721 Datasheet 19 April 4, 2016 Integrated Device Technology 2.3 Pinlist For a list-based version of Tsi721’s pin to signal mapping, see the Tsi721 Ballmap and Pinlist. 2.4 PCIe Signals Table 2: PCIe Signals Name Pin Type Description PCTP[3:0] PCTN[3:0] PCIE_O Differential transmit data for the PCIe port. PCRP[3:0] PCRN[3:0] PCIE_I Differential receive data for the PCIe port. PCCLKP PCCLKN DIFF_I PCIe reference clock input. When in PCIe common clock mode (CLKMOD pin is high, see the “Clocking” chapter in the Tsi721 User Manual), PCCLKP/N requires a clock frequency of 100 MHz. When in PCIe non-common clock mode (CLKMOD pin is low), PCCLKP/N requires a clock frequency as selected by CLKSEL[1:0], and must have the same clock frequency as REFCLKP/N. PCRSTOn IO It is an output for normal operation and an input during scan test mode. As an asynchronous active-low reset output, this pin is low when the following occurs: • The PCIe port detects hot reset • The PCIe port is DL_DOWN |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
