AD5100EVAL datasheet(15/32 Pages) AD

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Preliminary Technical Data

AD5100

Rev. PrJ | Page 15 of 32

Watchdog Input

The Watch-Dog Input (WDI) circuit attempts to reset the

system to a known good state if a software or hardware glitch

renders the system processor inactive for a duration that is

longer than the timeout period. There is an 8-step

programmable timeout period from 100ms to 2000ms.The

watchdog circuit is independent of the CPU clock that the

watchdog is monitoring.

Watchdog is disabled during power-up. WDI starts

monitoring once the RESET is high. Unique to AD5100, it

provides a Standard or Advance Watchdog monitoring

function. In the defaulted Standard Watchdog mode, if WDI

remains either high or low for longer than the timeout

period, a reset pulse is generated in an attempt to allow the

system processor to re-establish the WDI signal. The reset

pulses continue indefinitely until a valid watchdog signal, a

rising or falling edge signal at the WDI, is received. The

internal watchdog timer clears whenever reset is asserted.

The Standard WDI and RESET timing diagrams are shown in

Figure 12.

RESET

WDI

WDR

Continuous pulses until WD awakes

reset pulse

WDI

RESET

WDI

WDR

Continuous pulses until WD awakes

reset pulse

WDI

Figure 12. Standard Watchdog – Pulsing Reset Until Watchdog Awakes.

On the other hand, the AD5100 can be programmed to an

Advance Watchdog mode such that when the watchdog

remains inactive longer than three times the watchdog

timeout period, at the forth time the SHDN and RESET will be

asserted and released after 1 second. These actions repeat

indefinitely, unless it is interferred by the user, if the

processor is not responding. The Advance WDI and RESET

timing diagrams are shown in Figure 13.

RESET

SHDN

WDI

WD_SHDN

WDR

3 reset pulses

1 reset pulse

Shutdown at 4th reset pulse

Release after 1s

WDI

RESET

SHDN

WDI

WD_SHDN

WDR

3 reset pulses

1 reset pulse

Shutdown at 4th reset pulse

Release after 1s

WDI

Figure 13. Advance Watchdog –

SHDN Asserted After Three Trials of Reseting the Watchdog. SHDN Released After 1 second and the cycle repeats.

The range of Watchdog Timeout is shown in Table 6a and

the programming code of the selected-timeout is found in

Table 6b. The default timeout is 1500ms.

If WDI is floating, the watchdog is disabled by default.

However, floating watchdog can be enabled through I2C

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