TMPR4925 datasheet(50/590 Pages) TOSHIBA

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Chapter 1 Features

1-4

1.2.2.3

SDRAM Controller (SDRAMC)

The SDRAM Controller generates necessary control signals for the SDRAM interface. It has

four channels and can handle up to 2G bytes (512 MB/channel) of memory by supporting a variety

of memory configurations.

•

Memory clock frequency: 80 MHz (divided by 2.5)

•

4 sets of independent memory channels

•

Supports 16M-/64M-/128M-/256M-/512M-bit SDRAM with 2/4 bank size availability

•

Supports Single Data Rate (SDR) SDRAM and SyncFlash

memory

•

Supports use of Registered DIMM

•

Supports 32-/16-bit data bus sizing on a per channel basis

•

Supports specification of SDRAM timing on a per channel basis

•

Supports critical word first access of TX49/H2 core

•

Low power mode: selectable between self-refreshing and pre-charge power-down

1.2.2.4

PCI Controller (PCIC)

The TX4925 contains a PCI Controller that complies with PCI Local Bus Specification

Revision 2.2.

•

Compliance with PCI Local Bus Specification Revision 2.2

(Partly supports power management as optional function)

•

32-bit PCI interface featuring maximum PCI bus clock frequency of 33 MHz

•

Supports both target and initiator functions

•

Supports change of address mapping between internal bus and PCI bus

•

PCI bus arbiter enables connection of up 4 external bus masters

•

Supports booting of TX4925 from memory on PCI bus

•

1 channel of DMA controller dedicated to PCI controller (PDMAC)

1.2.2.5

Serial I/O Controller (SIO)

The TX4925 contains a 2-channels asynchronous serial I/O interface (full duplex UART).

•

2-channel full duplex UART

•

Built-in baud rate generator

•

FIFOs

8-bit x 8 transmitter FIFO

13-bit (8 data bits and 5 status bits) x 16 receiver FIFO

•

Supports DMA tranfer

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