TMPR4925 datasheet(94/590 Pages) TOSHIBA

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Chapter 5 Configuration Register

5-4

Bits

Mnemonic

Field Name

Description

TOE

Timeout Enable

for Bus Error

Timeout Enable for Bus Error (Initial value: 0, R/W)

Designates the state of the Bus Error time-out function.

0: Disable time out function.

1: Enable time out function.

PCIARB

PCI arbiter

PCI arbiter. (Initial value: ADDR[1], R)

Select PCI arbiter.

Latched from ADDR[1] at RESET.

L: 0: External arbiter

H: 1: Internal arbiter

12:8



Reserved



7:6

SYSSP

SYSCLK Speed

SYSCLK Speed (Initial value: ADDR[4:3], R)

Shows SYSCLK frequency.

LL: 00: SYSCLK speed = GBUSCLK speed/4

LH: 01: SYSCLK speed = GBUSCLK speed/3

HL: 10: SYSCLK speed = GBUSCLK speed/2

HH: 11: SYSCLK speed = GBUSCLK speed

5:4



Reserved

Note: These bits are always set to “11” (Initial value: 11, R/W).

PCTRCE

PC Trace Enable

PC Trace Enable (Initial value: TD0, R)

Shows whether PC Trace signals are enable or disable.

0: Disable

1: Enable

ENDIAN

Endian

Current Endian Setting (Initial value: ADDR[14], R)

Shows the endian mode.

L: 0: LITTLE ENDIAN

H: 1: BIG ENDIAN

WDRST

Watchdog Reset

Status

Watchdog Reset Status (Initial value: 0, R/W1C)

Indicates that a watchdog reset was generated.

0: No watchdog reset occur

1: Watchdog reset occurs

0UAEHOLD

UAE Address

Hold

UAE* Address Hold (Initial value: 1, R/W)

0: Address goes away during the same clock as UAE*.

1: Address is held one clock after the rising edge of UAE*.

Figure 5.2.1 Chip Configuration Register (CCFG) (2/2)

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