TMPR4925 datasheet(56/590 Pages) TOSHIBA

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Chapter 2 Block Diagram

2-2

Figure 2.1.1 shows a diagram of the TX4925. The each block is itemized below.

(1) TX49/H2 core

•

It is composed of CPU, System Control Coprocessor (CP0), Instruction Cache, Data Cache,

Floating-Point Unit (FPU), Write Buffer (WBU), Debug Support Unit (DSU) and G-Bus I/F.

− FPU: IEEE754 compatible single and double precision FPU

It is assigned as one of the coprocessor unit, CP1.

− I-Cache: Instruction Cache Memory, 16Kbyte, 4-Way set associative

− D-Cache: Data Cache Memory, 16Kbyte, 4-Way set associative Select write-back mode or

write-through(no write allocate/write allocate) mode for cache write policy.

− DSU: Debug Support Unit, It is used for on chip debugging module.

(2) EBUSC

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External Bus Controller, Provides 6-channels programmable Chip Selects, Supports ROMs (page-

mode ROM, mask ROM, EPROM and EEPROM), SRAMs, flash ROMs and I/O devices

(3) DMAC

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Direct Memory Access Controller, Supports transfers to and from both memory and

internal/external I/O devices

(4) SDRAMC

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SDRAM Controller, Supports 4-channels/80 MHz bus frequencies/16 or 32 bus width

(5) PCIC

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PCI-bus Controller, Compliance with PCI Local Bus Specification Revision 2.2, Supports 32-bit

PCI bus interface and 33 MHz operation

(6) SIO

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Serial I/O, Supports 2-channels for universal asynchronous receiver/transmitters

(7) TMR

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Timer/Counter, Supports 3-channels

(8) PIO

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Parallel I/O, Supports 32-bit of shared PIO pins

(9) ACLC

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AC-Link Controller, Compliance with Audio CODEC ’97 Revision 2.1 (AC ’97)

(10) IRC

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Interrupt Controller

(11) CHI

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High–speed serial Concentration Highway Interface

(12) SPI

•

Serial Peripheral Interface, Supports full-duplex synchronous serial data transfers

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