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TMPR4925 Datasheet(PDF) 52 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 52 Page - Toshiba Semiconductor |
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52 / 590 page  Chapter 1 Features 1-6 1.2.2.10 high-speed serial Concentration Highway Interface (CHI) The TX4925 has a CHI module. • Contents logic for interfacing to external full-duplex serial time-division-multiplexed (TDM) communication peripherals • Supports ISDN line interface chips and other PCM/TDM serial devices • Programmable CHI Interface (numbers of channels, frame rate, bit rate, etc.) • supports data rates up to 4.096 Mbps 1.2.2.11 Serial Peripheral Interface (SPI) The TX4925 has an SPI module. • full-duplex, synchronous serial data transfers (data in/out, and clock signals) • 8-bit or 16-bit data word lengths • Programmable SPI baud rate 1.2.2.12 NAND Flash Controller The TX4925 has a NAND Flash memory Controller. • Controlled NAND Flash I/F by Setting Register • Supports On-chip ECC (Error Correct Circuit) calculating circuits 1.2.2.13 PCMCIA Interface (PCMCIAI/F) The TX4925 has a 2 identical full PCMCIA ports. • Provide the control signals and accepts the status signals which conform to the PCMCIA version 2.1 standard • Appropriate connector keying and level-shifting buffers required for 3.3 V versus 5 V PCMCIA interface implementations 1.2.2.14 Real Time Clock (RTC) The TX4925 has an RTC module. • 44-bit up-counter • Interrupts on alarm, timer, and prior to RTC roll-over • Date managed by software 1.2.2.15 Power-down Mode The TX4925 contains support for implementation of power-down mode. • HALT mode (stopping CPU core clock) for TX49/H2 core block • Power-down mode (stopping input clock) for individual internal peripheral modules • RF (Reduced Frequency) Function (1/1, 1/2, 1/4, 1/8) |
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