TMPR4925 datasheet(72/590 Pages) TOSHIBA

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Chapter 3 Signals

3-14

Table 3.2.2 Boot Configuration Specified with the ADDR[19:0], TDO, UAE and SADDR10 Signals (2/2)

Signal

Description

Corresponding

Configuration

Determined at

ADDR[8:6]

Select Boot Memory

Selects boot memory.

HHH = Device connected to channel 0 of the external bus controller

(clock frequency division ratio: 1/1)

HHL = Device connected to channel 0 of the external bus controller

(clock frequency division ratio: 1/2)

HLH = Device connected to channel 0 of the external bus controller

(clock frequency division ratio: 1/3)

HLL = Reserved

LHH = PCI boot

LHL = Reserved

LLH = Reserved

LLL = SyncFlash memory connected to SDRAMC channel 0

EBCCR0.ME

RESET* deassert

edge

ADDR[5]

Boot ACK* Input

Specifies the access mode for external bus controller channel 0. If

SyncFlash is selected as a boot memory device, refer to Table 3.2.3.

L = ACK* Input Mode Enable

H = ACK* Input Mode Disable

EBCCR0.EACK

RESET* deassert

edge

ADDR[4:3]

Select SYSCLK Frequency

Specifies the division ratio of the SYSCLK frequency to the G-Bus clock

(GBUSCLK) frequency.

LL = 4 (SYSCLK frequency = GBUSCLK frequency/4)

LH = 3 (SYSCLK frequency = GBUSCLK frequency/3)

HL = 2 (SYSCLK frequency = GBUSCLK frequency/2)

HH = 1 (SYSCLK frequency = GBUSCLK frequency)

CCFG. SYSSP

PON* deassert edge

ADDR[2]

Reserved

This signal will not be set to 0 upon booting.

If Syncflash is selected as a boot memory device, refer to Table 3.2.3.



RESET*deassert

edge

ADDR[1]

PCI Arbiter Select

Selects a PCI bus arbiter.

H = Built-in PCI bus arbiter.

L = External PCI bus arbiter.

CCFG.PCIARB

RESET* deassert

edge

ADDR[0]

TX49/H2 Internal Timer Interrupt Disable

Specifies whether timer interrupts within the TX49/H2 core are enabled.

H = Disable timer interrupts within the TX49/H2 core.

L = Enable timer interrupts within the TX49/H2 core.

CCFG.TINTDIS

RESET* deassert

edge

TDO

PC Trace

Specifies whether PIO[31:20] and BC32K are used as PC trace signals.

H = Use as PIO[31:20] and BC32K

L = Use as TPC[3:1], PCST[7:0] and DCLK

CCFG.PCTRCE

PON* deassert edge

UAE

Reserved

Used for testing. Because this signal is used for setting a clock

frequency, ensure that the signal will not be set to 0 upon booting.

CCFG.bit[28]

PON* deassert edge

SADDR10

Reserved

Used for testing. Because this signal is used for setting a clock

frequency, ensure that the signal will not be set to 0 upon booting.



PON* deassert edge

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