TMPR4925 datasheet(93/590 Pages) TOSHIBA

93 / 590 page

Chapter 5 Configuration Register

5-3

5.2.1

Chip Configuration Register (CCFG)

0xE000

For the bit fields whose initial values are set by boot configuration (refer to Section 3.2), the initial

input signal level and the corresponding register value are indicated.

The following bits are Reserved (Read only). An explanation of the type and default was added so the

default is reflected in the Boot signal.

bit 31: R ~ADDR[10], bit 28: R UAE, bit 27: R ADDR[16]

bit 18: R ADDR[17], bit 12: R ADDR[19]

Reserved

BOOTME

PCIMODE

Reserved

TINTDIS

BEOW

R/W

R/W1C

: Type

ADDR[8:6]

ADDR[15]

ADDR[0]

: Initial value

765432

TOE

PCIARB

Reserved

SYSSP

Reserved

PCTRCE

ENDIAN WDRST UAEHOLD

R/W

R/W1C

R/W

: Type

~ADDR[1]

ADDR[4:3]

~TDO ADDR[14]

: Initial value

Bits

Mnemonic

Field Name

Description

31:27



Reserved



Reserved

Note: This bit is always set to “0”. (Initial value: 0, R/W)

25:24

Reduced

Frequency

Reduced Frequency (Initial value: 00, R/W)

These bits select the internal bus speed.

00: full speed

01: 1/2 speed

10: 1/4 speed

11: 1/8 speed

23:21

BOOTME

Boot Memory

Boot Memory (Initial value: ADDR[8:6], R)

Shows Boot Memory

000: SyncFlash

001: Reserved

010: Reserved

011: PCIC

100: Reserved

101: EBUSC ch0 at third speed

110: EBUSC ch0 at half speed

111: EBUSC ch0 at full speed

PCIMODE

PCI Mode

PCI Mode (Initial value: ADDR[15], R)

Shows the PCI operation mode.

L: Satellite mode

H: Host mode

19:18



Reserved



TINTDIS

TX49/H2 core

Timer Interrupt

Disable

TX49/H2 core Timer Interrupt Disable (Initial value: ADDR[0], R)

Shows whether TX49/H2 core Timer Interrupt is enable or disable.

L: Enable

H: Disable

BEOW

Bus Error on

Write

Bus Error on Write (Initial value: 0, R/W1C)

Indicates that a bus error was generated by a write operation of the TX49/H2 Core.

Writing a “1” clears the bit.

0: No error occur

1: Error occurs

Watchdog Timer

for Reset/NMI

Watchdog Timer for Reset/NMI (Initial value: 0, R/W)

Designates the connection of the Watchdog Timer.

0: Watchdog Timer Interrupt is connected to TX4925 internal NMI*.

1: Watchdog Timer Interrupt is connected to TX4925 internal Reset.

Figure 5.2.1 Chip Configuration Register (CCFG) (1/2)

TMPR4925 Datasheet(PDF) 93 Page - Toshiba Semiconductor

TMPR4925 Datasheet(HTML) 93 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL