PI7C8150ANDE datasheet(69/111 Pages) PERICOM

69 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 69 of 111

APRIL 2006 – Revision 1.1

PI7C8150A can start the transaction on the next PCI clock cycle by asserting P_FRAME_L

if P_GNT_L is still asserted.

If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the

last master that used the PCI bus. That is, PI7C8150A keeps the secondary bus grant

asserted to a particular master until a new secondary bus request comes along. After reset,

PI7C8150A parks the secondary bus at itself until transactions start occurring on the

secondary bus. Offset 48h, bit 1, can be set to 1 to park the secondary bus at PI7C8150A.

By default, offset 48h, bit 1, is set to 0. If the internal arbiter is disabled, PI7C8150A parks

the secondary bus only when the reconfigured grant signal, S_REQ_L[0], is asserted and

the secondary bus is idle.

CLOCKS

This chapter provides information about the clocks.

9.1

PRIMARY CLOCK INPUTS

PI7C8150A implements a primary clock input for the PCI interface. The primary interface

is synchronized to the primary clock input, P_CLK, and the secondary interface is

synchronized to the secondary clock. The secondary clock is derived internally from the

primary clock, P_CLK. PI7C8150A operates at a maximum frequency of 66 MHz

(33MHz for PI7C8150A-33).

9.2

SECONDARY CLOCK OUTPUTS

PI7C8150A has 10 secondary clock outputs, S_CLKOUT[9:0] that can be used as clock

inputs for up to nine external secondary bus devices. The S_CLKOUT[9:0] outputs are

derived from P_CLK. The secondary clock edges are delayed from P_CLK edges by a

minimum of 0ns. This is the rule for using secondary clocks:

Each secondary clock output is limited to no more than one load.

GENERAL PURPOSE I/O INTERFACE

The PI7C8150A implements a 4-pin general purpose I/O interface. During normal

operation, device specific configuration registers control the GPIO interface. The GPIO

interface can be used for the following functions:

During secondary interface reset, the GPIO interface can be used to shift in a 16-bit

serial stream that serves as a secondary bus clock disable mask.

Along with the GPIO[3] pin, a live insertion bit can be used to bring the PI7C8150A to

a halt through hardware, permitting live insertion of option cards behind the

PI7C8150A.

06-0057

PI7C8150ANDE Datasheet(PDF) 69 Page - Pericom Semiconductor Corporation