PI7C8150ANDE datasheet(9/111 Pages) PERICOM

9 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 9 of 111

APRIL 2006 – Revision 1.1

PACKAGE INFORMATION............................................................................ 109

18.1

208-PIN FQFP PACKAGE DIAGRAM ................................................................................ 109

18.2

256-BALL PBGA PACKAGE DIAGRAM ........................................................................... 110

18.3

PART NUMBER ORDERING INFORMATION.................................................................. 110

LIST OF TABLES

TABLE 2-1. PIN LIST – 208-PIN FQFP .......................................................................................................... 18

TABLE 2-2. PIN LIST – 256-PIN PBGA ......................................................................................................... 20

TABLE 3-1. PCI TRANSACTIONS ................................................................................................................... 22

TABLE 3-2. WRITE TRANSACTION FORWARDING......................................................................................... 23

TABLE 3-3. WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES .................................................... 26

TABLE 3-4. READ PREFETCH ADDRESS BOUNDARIES .................................................................................. 28

TABLE 3-5. READ TRANSACTION PREFETCHING .......................................................................................... 28

TABLE 3-6. DEVICE NUMBER TO IDSEL S_AD PIN MAPPING..................................................................... 32

TABLE 3-7. DELAYED WRITE TARGET TERMINATION RESPONSE................................................................. 37

TABLE 3-8. RESPONSE TO POSTED WRITE TARGET TERMINATION............................................................... 38

TABLE 3-9. RESPONSE TO DELAYED READ TARGET TERMINATION ............................................................. 38

TABLE 5-1. SUMMARY OF TRANSACTION ORDERING ................................................................................... 50

TABLE 6-1. SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT .......................................... 58

TABLE 6-2. SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT ............................................ 59

TABLE 6-3. SETTING PRIMARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT......................... 59

TABLE 6-4. SETTING SECONDARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT.................... 60

TABLE 6-5. ASSERTION OF P_PERR_L........................................................................................................ 60

TABLE 6-6. ASSERTION OF S_PERR_L........................................................................................................ 61

TABLE 6-7. ASSERTION OF P_SERR_L FOR DATA PARITY ERRORS ............................................................ 61

TABLE 10-1. GPIO OPERATION ................................................................................................................... 71

TABLE 10-2. GPIO SERIAL DATA FORMAT.................................................................................................. 71

TABLE 11-1. POWER MANAGEMENT TRANSITIONS ...................................................................................... 73

TABLE 16-1. TAP PINS .............................................................................................................................. 101

TABLE 16-2. JTAG BOUNDARY REGISTER ORDER .................................................................................... 103

LIST OF FIGURES

FIGURE 8-1

SECONDARY ARBITER EXAMPLE............................................................................................ 67

FIGURE 16-1

TEST ACCESS PORT BLOCK DIAGRAM ............................................................................... 100

FIGURE 17-1

PCI SIGNAL TIMING MEASUREMENT CONDITIONS ............................................................ 107

FIGURE 18-1

208-PIN FQFP PACKAGE OUTLINE..................................................................................... 109

FIGURE 18-2

256-PIN PBGA PACKAGE OUTLINE.................................................................................... 110

06-0057

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