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PI7C8150ANDE Datasheet(PDF) 21 Page - Pericom Semiconductor Corporation |
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PI7C8150ANDE Datasheet(HTML) 21 Page - Pericom Semiconductor Corporation |
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21 / 111 page  PI7C8150A 2-PORT PCI-TO-PCI BRIDGE Page 21 of 111 APRIL 2006 – Revision 1.1 Pin Number Name Type Pin Number Name Type Pin Number Name Type J2 GPIO[2] TS J3 GPIO[3] TS J4 VDD P J5 VDD P J6 VSS P J7 VSS P J8 VSS P J9 VSS P J10 VSS P J11 VSS P J12 VDD P J13 VDD P J14 RESERVED - J15 TDI I J16 RESERVED - K1 GPIO[0] TS K2 S_CLKOUT[0] O K3 S_CLKOUT[1] O K4 VDD P K5 VDD P K6 VSS P K7 VSS P K8 VSS P K9 VSS P K10 VSS P K11 VSS P K12 VDD P K13 VDD P K14 P_VIO I K15 MSK_IN I K16 CFG66 SCAN_EN_H I L1 S_CLKOUT[2] O L2 S_CLKOUT[3] O L3 S_CLKOUT[5] O L4 S_CLKOUT[6] O L5 VDD P L6 VSS P L7 VSS P L8 VSS P L9 VSS P L10 VSS P L11 VSS P L12 VDD P L13 P_AD[4] TS L14 P_AD[2] TS L15 P_AD[1] TS L16 P_AD[0] TS M1 S_CLKOUT[4] O M2 S_CLKOUT[8] O M3 S_CLKOUT[9] O M4 P_CLK I M5 VSS P M6 VDD P M7 VDD P M8 VDD P M9 VDD P M10 VDD P M11 VDD P M12 VSS P M13 P_AD[6] TS M14 P_AD[7] TS M15 P_AD[5] TS M16 P_AD[3] TS N1 S_CLKOUT[7] O N2 BPCCE I N3 P_AD[31] TS N4 VSS P N5 P_AD[28] TS N6 P_AD[25] TS N7 VDD P N8 VDD P N9 VDD P N10 VDD P N11 P_PAR TS N12 P_AD[11] TS N13 VSS P N14 VSS P N15 P_AD[8] TS N16 P_CBE_L[0] TS P1 P_RESET_L I P2 P_REQ_L TS P3 VSS P P4 VSS P P5 P_AD[27] TS P6 P_IDSEL I P7 P_AD[22] TS P8 P_AD[18] TS P9 P_FRAME_L STS P10 P_DEVSEL_L STS P11 P_SERR_L OD P12 P_AD[14] TS P13 VDD P P14 VSS P P15 VDD P P16 P_AD[9] TS R1 P_GNT_L I R2 VSS P R3 VDD P R4 VSS P R5 P_AD[24] TS R6 P_CBE_L[3] TS R7 P_AD[20] TS R8 P_AD[17] TS R9 P_CBE_L[2] TS R10 P_TRDY_L STS R11 P_LOCK_L STS R12 P_AD[15] TS R13 P_AD[12] TS R14 P_M66EN I R15 VSS P R16 MS1 P T1 VSS P T2 P_AD[30] TS T3 VDD P T4 P_AD[29] TS T5 P_AD[26] TS T6 P_AD[23] TS T7 P_AD[21] TS T8 P_AD[19] TS T9 P_AD[16] TS T10 P_IRDY_L STS T11 P_STOP_L STS T12 P_PERR_L STS T13 P_CBE_L[1] TS T14 P_AD[13] TS T15 P_AD[10] TS T16 VSS P 3 PCI BUS OPERATION This Chapter offers information about PCI transactions, transaction forwarding across PI7C8150A, and transaction termination. The PI7C8150A has two 128-byte FIFO’s for buffering of upstream and downstream transactions. These hold addresses, data, commands, and byte enables that are used for write transactions. The PI7C8150A also has an additional four 128-byte FIFO’s that hold addresses, data, commands, and byte enables for read transactions. 06-0057 |
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