PI7C8150ANDE datasheet(94/111 Pages) PERICOM

94 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 94 of 111

APRIL 2006 – Revision 1.1

Bit

Function

Type

Description

Secondary

MEMW

Command Alias

Enable

R/W

Controls PI7C8150A’s detection mechanism for matching non-posted

memory write retry cycles from the initiator on the primary interface

0: exact matching for non-posted memory write retry cycles from

initiator on the secondary interface

1: alias MEMWI to MEMW for non-posted memory write retry

cycles from initiator on the secondary interface

Reset to 0

5:6

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0.

Primary

MEMWI

Command Alias

Enable

R/W

Controls PI7C8150A’s detection mechanism for matching non-posted

memory write and invalidate cycles from the initiator on the primary

interface

0: When accepting MEMWI command at the primary interface,

PI7C8150A converts MEMWI to MEMW command on the

secondary interface

1: Disconnects MEMWI command at aligned cache line boundaries

Secondary

MEMWI

Command Alias

Enable

R/W

Controls PI7C8150A’s detection mechanism for matching non-posted

memory write and invalidate cycles from the initiator on the

secondary interface

0: When accepting MEMWI command at the secondary interface,

PI7C8150A converts MEMWI to MEMW command on the primary

interface

1: Disconnects MEMWI command at aligned cache line boundaries

Enable Long

Request

R/W

Controls PI7C8150A’s ability to enable long requests for lock cycles

0: normal lock operation

1: enable long request for lock cycle

Reset to 0

Enable

Secondary To

Hold Request

Longer

R/W

Controls PI7C8150A’s ability to enable the secondary bus to hold

requests longer.

0: internal secondary master will release REQ_L after FRAME_L

assertion

1: internal secondary master will hold REQ_L until there is no

transactions pending in FIFO or until terminated by target

Reset to 1

Enable Primary

To Hold Request

Longer

R/W

Controls PI7C8150A’s ability to hold requests longer at the Primary

Port.

0: internal Primary master will release REQ_L after FRAME_L

assertion

1: internal Primary master will hold REQ_L until there is no

transactions pending in FIFO or until terminated by target

Reset to 1

15:12

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0.

06-0057

PI7C8150ANDE Datasheet(PDF) 94 Page - Pericom Semiconductor Corporation

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