UPD750004 datasheet(28/86 Pages) RENESAS

28 / 86 page

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Data Sheet U10738EJ3V2DS

6.6

CLOCK TIMER

The

µPD750008 contains one channel for a clock timer. The clock timer provides the following functions:

• Sets the test flag (IRQW) with a 0.5 sec interval. The standby mode can be released by IRQW.

• The 0.5 second interval can be generated from either the main system clock (4.194304 MHz) or subsystem clock

(32.768 kHz).

• The time interval can be made 128 times faster (3.91 ms) by selecting the fast mode. This is convenient for

program debugging, testing, etc.

• Any of the frequencies 2.048 kHz, 4.096 kHz, and 32.768 kHz can be output to the P23/BUZ pin. This can be

used for beep and system clock frequency trimming.

• The frequency divider circuit can be cleared so that a zero-second start of the clock can be made.

Fig. 6-5

Clock Timer Block Diagram

( ) is for fX = 4.194304 MHz, fXT = 32.768 kHz.

P23/BUZ

Internal bus

Selector

From the

clock

generator

128

(32.768 kHz)

fXT

(32.768 kHz)

Selector

Frequency divider

Selector

INTW

IRQW

set signal

2 Hz

0.5 sec

WM7

WM5

WM4

WM3

WM2

WM1

WM0

P23 output

latch

Bit 2 of PMGB

PORT2.3

Output buffer

Clear

(32.768 kHz)

Bit test instruction

Port 2 input/

output mode

(4 kHz) (2 kHz)

(256 Hz: 3.91 ms)

UPD750004 Datasheet(PDF) 28 Page - Renesas Technology Corp

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