DSP56367 datasheet(61/100 Pages) FREESCALE

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Serial Host Interface SPI Protocol Timing

DSP56367 Technical Data, Rev. 2.1

Freescale Semiconductor

3-37

Figure 3-26 Host DMA Read Timing Diagram

3.12

Serial Host Interface SPI Protocol Timing

Table 3-16 Serial Host Interface SPI Protocol Timing

No.

Characteristics1

Mode

Filter

Mode

Expression2

Min

Max

Unit

140

Tolerable spike width on clock or data in

—

Bypassed

Narrow

Wide

—

100

141

Minimum serial clock cycle = tSPICC(min)

Master

Bypassed

Narrow

Wide

× TC+46

× TC+152

× TC+223

86.2

192.2

263.2

—

142

Serial clock high period

Master

Bypassed

Narrow

Wide

0.5

× tSPICC –10

0.5

× tSPICC –10

0.5

× tSPICC –10

126.5

—

Slave

Bypassed

Narrow

Wide

2.5

× TC + 12

2.5

× TC + 102

2.5

× TC + 189

28.8

118.8

205.8

—

143

Serial clock low period

Master

Bypassed

Narrow

Wide

0.5

× tSPICC –10

0.5

× tSPICC –10

0.5

× tSPICC –10

—

Slave

Bypassed

Narrow

Wide

2.5

× TC + 12

2.5

× TC + 102

2.5

× TC + 189

28.8

118.8

205.8

—

326

317

318

327

328

329

Data

Valid

HOREQ

(Output)

HACK

(Input)

H0-H7

(Output)

RXH

Read

343

342

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