RT5510WSC datasheet(28/52 Pages) RICHTEK

28 / 52 page

RT5510

is a registered trademark of Richtek Technology Corporation

www.richtek.com

DS5510-00

October

2019

If battery voltage returns to a hysteresis level, ClipThres will increase by a rate of CLIPRR to a certain level which is

defined by VBCPS, CPSLP and VBAT. The battery voltage hysteresis can be set via BVHYS register.

VBAT (Thr) + BVHYS

VBAT (Thr)

CLIPRR

ClipThres

Figure 22. Clip Threshold Depend on VBAT

Hard Clipping

When Hard clip is enabled (Register 0x24 bit 8), if the digital signal is larger than HARD_CLIP_TH, the signal will be

clamped to HARD_CLIP_TH.

Table 11. Hard Clipping

Bits

Bits Name

Description

0x24

HARD_CLIP_EN

0 : Disable hard clipping

1 : Enable hard clipping (default)

7:0

HARD_CLIP_TH

Hard clip threshold if HARD_CLIP_EN = 1

downward, 12 to

115.5dB in 0.5dB

step, (default 00000000 = 12dB)

e.g. 00000001 = 11.5dB

3dB

0dB

3dB

Clip level =

3dB

Clip level = 0dB

Clip level = 3dB

Figure 23. Signal Hard Clipping

DRE

In the signal path, the noise floor of SPK output is related to the analog gain. If decreasing the analog gain, the noise

floor decreases, and vice versa. However, increasing the digital gain will not affect the noise floor. To help

eliminating unwanted low level noise caused by analog circuit when incoming signal is below a certain threshold, a

DRE technique is used. The DRE, Dynamic Range Expansion, stands for expanding the dynamic range of a signal.

Any signal before entering analog circuit below the threshold is expanded by the specified ratio, and also the analog

end is compressed by the inverse of this ratio.

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