TAS5504_06 datasheet(83/96 Pages) TI

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Serial Control Interface Register Definitions

SLES123 − October 2004

TAS5504

6.24 DRC Bypass Registers (0xA2, 0xA3, 0xA8, 0xA9)

DRC bypass/inline for channels 1, 2, 3, and 4 are mapped into registers 0xA2, 0xA3, 0xA8, and 0xA9. 8−bytes

are written for each channel. Each gain coefficient is in 28-bit (5.23) format so 0x00800000 is a gain of 1. Each

gain coefficient is written as a 32-bit word with the upper 4 bits not used.

To enable DRC for a given channel (with unity gain), bypass = 0x00000000 and inline = 0x00800000.

To disable DRC for a given channel, bypass = 0x00800000 and inline = 0x00000000.

Table 6−26. DRC Bypass Registers Format (0xA2−0xA9)

TOTAL

BYTES

CONTENTS

INITIALIZATION

VALUE

Channel bass DRC bypass

U (31:28), bypass (27:24), bypass (23:16), bypass (15:8), bypass (7:0) 0x00, 0x80, 0x00, 0x00

Channel DRC inline

U (31:28), inline (27:24), inline (23:16), inline (15:8), inline (7:0)

0x00, 0x00, 0x00, 0x00

6.25 4x2 Output Mixer Registers (0xAA and 0xAB)

Output mixers for channels 1 and 2 map to registers 0xAA and 0xAB.

Total data per register is 8 bytes.

Table 6−27. Output Mixer Control Register Format (Upper 4 Bytes)

D31

D30

D29

D28

D27

D26

D25

D24

FUNCTION

Select channel 1 to output mixer

Select channel 2 to output mixer

Select channel 3 to output mixer

Select channel 4 to output mixer

G27

G26

G25

G24

Selected channel gain (upper 4 bits)

D23

D22

D21

D20

D19

D18

D17

D16

FUNCTION

G23

G22

G21

G20

G19

G18

G17

G16

Selected channel gain (continued)

D15

D14

D13

D12

D11

D10

FUNCTION

G15

G14

G13

G12

G11

G10

Selected channel gain (continued)

FUNCTION

Selected channel gain (lower 8 bits)

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