SST25VF040B datasheet(10/31 Pages) MICROCHIP

10 / 31 page

 2005-2020 Microchip Technology Inc.

DS20005051F-page 10

SST25VF040B

5.2

High-Speed Read (50 MHz)

The High-Speed Read instruction, supporting up to

50 MHz Read, is initiated by executing an 8-bit com-

mand, 0BH, followed by address bits [A23-A0] and a

dummy byte. CE# must remain active-low for the dura-

tion of the High-Speed Read cycle. See Figure 5-2 for

the High-Speed Read sequence.

Following a dummy cycle, the High-Speed Read

instruction outputs the data starting from the specified

address location. The data output stream is continuous

through all addresses until terminated by a low-to-high

transition on CE#.

The internal address pointer will automatically incre-

ment until the highest memory address is reached.

Once the highest memory address is reached, the

address pointer will automatically increment to the

beginning (wrap-around) of the address space. Once

the data from address location 7FFFFH has been read,

the next output will be from address location 00000H.

FIGURE 5-2:

HIGH-SPEED READ SEQUENCE

5.3

Byte Program

The Byte Program instruction programs the bits in the

selected byte to the desired data. The selected byte

must be in the erased state (FFH) when initiating a Pro-

gram operation. A Byte Program instruction applied to

a protected memory area will be ignored.

Prior to any write operation, the Write Enable (WREN)

instruction must be executed. CE# must remain

active-low for the duration of the Byte Program instruc-

tion.

The Byte Program instruction is initiated by executing

an 8-bit command, 02H, followed by address bits

[A23-A0]. Following the address, the data is input in

order from MSb (bit 7) to LSb (bit 0). CE# must be

driven high before the instruction is executed. The user

may poll the BUSY bit in the software STATUS register

or wait TBP for the completion of the internal self-timed

Byte Program operation. See Figure 5-3 for the Byte

Program sequence.

FIGURE 5-3:

BYTE PROGRAM SEQUENCE

Note:

X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH)

CE#

SCK

ADD.

012 34 5

6 7 8

ADD.

High-Impedance

15 16

23 24

31 32

39 40

47 48

55 56

63 64

N+2

N+3

N+4

N+1

MSb

MODE 0

MODE 3

DOUT

71 72

DOUT

CE#

SCK

ADD.

0 1 234 5 6 78

ADD.

DIN

15 16

23 24

31 32

MODE 0

MODE 3

SST25VF040B Datasheet(PDF) 10 Page - Microchip Technology

SST25VF040B Datasheet(HTML) 10 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Datasheet Download

Link URL