SST25VF040B datasheet(14/31 Pages) MICROCHIP

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DS20005051F-page 14

SST25VF040B

FIGURE 5-10:

64-KBYTE BLOCK ERASE

SEQUENCE

5.9

Chip Erase

The Chip Erase instruction clears all bits in the device

to FFH. A Chip Erase instruction will be ignored if any

of the memory area is protected. Prior to any Write

operation, the Write Enable (WREN) instruction must be

executed. CE# must remain active-low for the duration

of the Chip Erase instruction sequence. The Chip

Erase instruction is initiated by executing an 8-bit com-

mand, 60H or C7H. CE# must be driven high before the

instruction is executed. The user may poll the BUSY bit

in the software STATUS register or wait TCE for the

completion of the internal self-timed Chip Erase cycle.

See Figure 5-11 for the Chip Erase sequence.

FIGURE 5-11:

CHIP ERASE SEQUENCE

5.10

Read STATUS Register (RDSR)

The Read STATUS Register (RDSR) instruction allows

reading of the STATUS register. The STATUS register

may be read at any time even during a write (program/

erase) operation. When a write operation is in prog-

ress, the BUSY bit may be checked before sending any

new commands to assure that the new commands are

properly received by the device. CE# must be driven

low before the RDSR instruction is entered and remain

low until the status data is read. Read STATUS register

is continuous with ongoing clock cycles until it is termi-

nated by a low-to-high transition of the CE#. See

Figure 5-12 for the RDSR instruction sequence.

FIGURE 5-12:

READ STATUS REGISTER (RDSR) SEQUENCE

5.11

Write Enable (WREN) Sequence

The Write Enable (WREN) instruction sets the Write

Enable Latch bit in the STATUS register to ‘1’ allowing

write operations to occur. The WREN instruction must be

executed prior to any write (program/erase) operation.

The WREN instruction may also be used to allow execu-

tion of the Write STATUS Register (WRSR) instruction;

however, the Write Enable Latch bit in the STATUS reg-

ister will be cleared upon the rising edge CE# of the

WRSR instruction. CE# must be driven high before the

WREN instruction is executed.

FIGURE 5-13:

WRITE ENABLE (WREN)

SEQUENCE

CE#

SCK

ADDR

0 1 234 5 6 78

ADDR

15 16

23 24

MODE 0

MODE 3

CE#

SCK

0 1 234 5 6 7

60 or C7

MODE 0

MODE 3

SCK

CE#

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0

High-Impedance

MSb

CE#

SCK

0 1 234 5 6 7

MODE 0

MODE 3

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