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WM8593 Datasheet(PDF) 51 Page - Wolfson Microelectronics plc |
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WM8593 Datasheet(HTML) 51 Page - Wolfson Microelectronics plc |
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51 / 98 page  Product Preview WM8593 w PP Rev 1.0 January 2007 51 UPDATE FUNCTION To prevent clock contention issues during setup of the digital audio interface mux, an update system has been implemented. This allows the registers to be configured as required and the update to be applied with the last register write synchronise the configuration of the digital audio mux. An update can be generated using any of the update bits shown in Table 39. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R37 AIF_MUX1 25h 10 PORT1_ UPD R38 AIF_MUX2 26h 10 PORT2_ UPD R39 AIF_MUX3 27h 10 PORT3_ UPD R40 AIF_MUX4 28h 10 PORT4_ UPD R41 AIF_MUX5 29h 10 PORT5_ UPD R42 AIF_MUX6 2Ah 10 DAC1_ UPD R43 AIF_MUX7 2Bh 10 DAC2_ UPD R44 AIF_MUX8 2Ch 10 ADC_ UPD 0 Update 0 = Latch corresponding settings into Register Map but do not update 1 = Latch corresponding settings into Register Map and update all simultaneously Table 39 Audio Interface Mux Update Bits DETAILS ON CLOCK SWITCHING In order to avoid short clock pulses (glitches) when switching between two independent clock sources, the MCLK and BCLK switching is carefully controlled within the WM8593 using various feedback and logic mechanisms. This controlled switching applies to all MCLK and BCLK digital audio port pins, and also when switching MCLK and BCLK sources in the ADC, DAC1 and DAC2 audio interfaces. Example: Switching from MCLK2 to MCLK3 using the MCLK4 pin CLK_A is applied to the MCLK2 pin, and CLK_B is applied to the MCLK3 pin. Initially, MCLK4_SEL[2:0]=001, so CLK_A is output on the MCLK4 pin. To change the output clock to CLK_B, set MCLK4_SEL[2:0]=010. The logic waits until CLK_A (MCLK2 pin) is low then disconnects CLK_A from the output (MCLK4) pin. The output pin (MCLK4) now outputs logic 0 for two rising edges of CLK_B (MCLK3 pin) before starting to output CLK_B. This behaviour is shown in Figure 23: |
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