WM8593 datasheet(89/98 Pages) WOLFSON

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WM8593

PP Rev 1.0 January 2007

R44 (2Ch) – Audio Interface MUX Configuration Register 8 (AIF_MUX8)

Bit #

Read

Write

N/A

ADC_UPD

N/A

Default

Bit #

Read

Write

N/A

ADCWORDCLK_SEL[2:0]

ADCMCLK_SEL[2:0]

ADC_

FORCE

Default

N/A = Not Applicable (no function implemented)

Function

Description

ADC_FORCE

Force ADC Clocks to Change

0 = Wait until clocks are safe before switching between clock sources

1 = Force clock sources to change immediately

See Table 40 for details of use.

ADCMCLK_SEL[2:0]

ADCMCLK Select

000 = Use MCLK1

001 = Use MCLK2

010 = Use MCLK3

011 = Use MCLK4

100 = Use MCLK5

101 to 111 = Reserved

ADCWORDCLK_

SEL[2:0]

ADCBCLK and ADCLRCLK Select

000 = Use BCLK1 and LRCLK1

001 = Use BCLK2 and LRCLK2

010 = Use BCLK3 and LRCLK3

011 = Use BCLK4 and LRCLK4

100 = Use BCLK5 and LRCLK5

101 = Use DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode)

110 = Use DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode)

111 = Output ADCBCLK and ADCBCLK (when ADC is master mode)

ADC_UPD

ADC Clock Update

0 = Latch corresponding ADC clock settings into Register Map but do not update

1 = Latch corresponding ADC clock settings into Register Map and update all simultaneously

Figure 60 R44 – Audio Interface MUX Configuration Register 8

WM8593 Datasheet(PDF) 89 Page - Wolfson Microelectronics plc

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