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WM8593 Datasheet(PDF) 58 Page - Wolfson Microelectronics plc |
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WM8593 Datasheet(HTML) 58 Page - Wolfson Microelectronics plc |
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58 / 98 page  WM8593 Product Preview w PP Rev 1.0 January 2007 58 REGISTER MAP D ec A ddr Hex A ddr Name 15 14 13 12 11 10 98 76 54 32 1 0 H ex D efault 0 00 DEVICE_ID 0x8594 101 REVISION 00 00 00 00 0x0000 2 02 DAC1_CTRL1 00 00 DAC1_MUTE DAC1 _EN DAC1_ZCEN DAC1_DEEMPH DAC1_LRP DAC1_BCP 0x008A 3 03 DAC1_CTRL2 00 00 00 000 0 0x0000 4 04 DAC1_CTRL3 00 00 00 000 00 00 00 DAC1_MSTR 0x0000 5 05 DAC1L_VOL 00 00 00 0 DAC1 L_VU 0x00C8 6 06 DAC1R_VOL 0 00 00 00 DAC1 R_VU 0x00C8 7 07 DAC2_CTRL10 0 0 0 DAC2_MUTE DAC2_EN DAC2_ZCEN DAC2_DEEMPH DAC2_LRP DAC2_BCP 0x008A 8 08 DAC2_CTRL2 0 00 00 00 0 0 0 0x0000 9 09 DAC2_CTRL3 0 0 0 0 0 0 000 00 00 00 DAC2_MSTR 0x0000 10 0A DAC2L_VOL 0 0 0 0 0 0 0 DAC2L_VU 0x00C8 110B DAC2R_VOL 0 0 0 0 0 0 0 DAC2R_VU 0x00C8 12 0C ENABLE 0 0 0 0 0 0 000 00 00 00 GLOBAL_EN 0x0000 13 0D ADC_CTRL10 0 ADC_ZC_EN ADC_HPD ADCL_INV ADCR_INV ADC_LRSWAP ADC_EN ADC_LRP ADC_BCP 0x200A 14 0E ADC_CTRL2 00 00 00 000 0x0000 15 0F ADC_CTRL3 00 00 00 000 00 00 0 ADC_MSTR 0x0000 16 10 ADCL_VOL 0 00 00 00 ADCL_VU 0x00C3 17 11 ADCR_VOL 0 0 0 0 0 0 0 ADCR_VU 0x00C3 19 13 PGA1L_VOL 00 00 00 0 PGA1 L_VU 0x000C 20 14 PGA1R_VOL 0 00 00 00 PGA1 R_VU 0x000C 211 5 PGA2L_VOL 0 0 0 0 0 0 0 PGA2L_VU 0x000C 22 16 PGA2R_VOL 0 0 0 0 0 0 0 PGA2R_VU 0x000C 23 17 PG3L_VOL 0 0 0 0 0 0 0 PGA3L_VU 0x000C 24 18 PGA3R_VOL 0 0 0 0 0 0 0 PGA3R_VU 0x000C 25 19 PGA_CTRL1 0 0 0 0 0 0 0 0 PGA3R_ZC PGA3L_ZC PGA2R_ZC PGA2L_ZC PGA1R_ZC PGA1L_ZC ATTACK_BYPASSDECAY_BYPASS 0x00FC 26 1APGA_CTRL2 0 0 0 JD_PGA3R_M UTE JD_PGA3 L_M UTE JD_PGA2R_M UTE JD_PGA2 L_M UTE JD_PGA1R_M UTE JD_PGA1L_M UTE VOUT3R_MUTE VOUT3L_MUTE VOUT2R_MUTE VOUT2L_MUTE VOUT1R_MUTE VOUT1L_MUTE MUTE_ALL 0x007E 27 1B GEN 0 0 0 0 0 0 0 0 0 AUTO_INC JD_INV GPIO2_APP GPIO1_APP 0x0048 28 1C INPUT_CTRL10 0 0 0 0x0000 29 1D INPUT_CTRL2 0 0 0 0 0x0000 30 1E INPUT_CTRL3 0 0 0 0 0 ADC_SWITCH_EN 0x0008 311 F INPUT_CTRL4 0 0 0 0 0 0 0 0 ADCR_AMP_EN ADCL_AMP_EN PGA3R_EN PGA3L_EN PGA2R_EN PGA2L_EN PGA1R_EN PGA1L_EN 0x0000 32 20 OUTPUT_CTRL10 0 0 0 0 0 0 0x0088 33 21OUTPUT_CTRL2 0 0 0 0 0 0 0 0x0163 34 22 OUTPUT_CTRL3 0 0 0 VOUT3R_EN VOUT3L_EN VOUT2R_EN VOUT2L_EN VOUT1R_EN VOUT1L_EN APE_B VOUT3R_TRI VOUT3L_TRI VOUT2R_TRI VOUT2L_TRI VOUT1R_TRI VOUT1L_TRI 0x0040 35 23 BIAS 0 0 0 0 0 0 0 0 BIAS_EN SOFT_ST BUFIOEN FAST_EN VMIDTOG POBCTRL 0x0010 36 24 PGA_CTRL_3 0 0 0 0 0 PGA_UPD 0 0 0 0 0 0 PGA_SAFE_SW 0x0002 37 25 AIF_MUX10 0 0 0 0 PORT1 _UPD PORT1_FORCE 0x0000 38 26 AIF_MUX2 0 0 0 0 0 PORT2_UPD PORT2_FORCE 0x0092 39 27 AIF_MUX3 0 0 0 0 0 PORT3_UPD PORT3_FORCE 0x0124 40 28 AIF_MUX4 0 0 0 0 0 PORT4_UPD PORT4_FORCE 0x01B6 4129 AIF_MUX5 0 0 0 0 0 PORT5_UPD PORT5_FORCE 0x0248 42 2A AIF_MUX6 0 0 0 0 0 DAC1_UPD DAC1_FORCE 0x0092 43 2B AIF_MUX7 0 0 0 0 0 DAC2_UPD DAC2_FORCE 0x0092 44 2C AIF_MUX8 0 0 0 0 0 ADC_UPD ADC_FORCE 0x0248 45 2D AIF_MUX9 0 0 0 0 0 GPIO1_UPD 000 00 0 0 0x0000 46 2E AIF_MUX10 0 0 0 0 0 GPIO2_UPD 0 0 0 0 0 0 0 0x0000 Read: DEVICE_ID[15:0] / Write: SW_RST REVNUM[7:0] DAC1_OP_MUX[1:0] DAC1_WL[1:0] DAC1_FMT[1:0] DAC1_SR[2:0] DAC1L_VOL[7:0] DAC1R_VOL[7:0] ADC_AMP_VOL[1:0] DAC2L_VOL[7:0] DAC2R_VOL[7:0] ADCL_VOL[7:0] ADCR_VOL[7:0] PGA1L_VOL[7:0] PGA1R_VOL[7:0] DAC2_OP_MUX[1:0] DAC2_WL[1:0] DAC2_FMT[1:0] DAC2_SR[2:0] DAC2_BCLKDIV[2:0] ADC_DATA_SEL[1:0] ADC_WL[1:0] ADC_FMT[1:0] ADC_BCLKDIV[2:0] ADC_SR[2:0] PGA2L_VOL[7:0] PGA2R_VOL7:0] PGA3L_VOL[7:0] PGA3R_VOL[7:0] PGA_SR[2:0] PGA2L_IN_SEL[3:0] PGA1R_IN_SEL[3:0] PGA1L_IN_SEL[3:0] PGA3L_IN_SEL[3:0] PGA2R_IN_SEL[3:0] ADCR_SEL[3:0] ADCL_SEL[3:0] DAC1_BCLKDIV[2:0] VMID_SEL[1:0] PGA_SEL[2:0] VOUT2L_SEL[2:0] VOUT1R_SEL[2:0] VOUT1L_SEL[2:0] VOUT3R_SEL[2:0] VOUT3L_SEL[2:0] VOUT2R_SEL[2:0] PGA3R_IN_SEL[3:0] MCLK1_SEL[2:0] WORDCLK1_SEL[2:0] DIO1_SEL[2:0] DIO2_SEL[2:0] WORDCLK2_SEL[2:0] MCLK2_SEL[2:0] DIO3_SEL[2:0] WORDCLK3_SEL[2:0] MCLK3_SEL[2:0] DIO4_SEL[2:0] WORDCLK4_SEL[2:0] MCLK4_SEL[2:0] DIO5_SEL[2:0] WORDCLK5_SEL[2:0] MCLK5_SEL[2:0] DAC1DIN_SEL[2:0] DAC1WORDCLK_SEL[2:0] DAC1MCLK_SEL[2:0] GPIO1_SEL[2:0] GPIO2_SEL[2:0] DAC2DIN_SEL[2:0] DAC2WORDCLK_SEL[2:0] DAC2MCLK_SEL[2:0] ADCDOUT_SEL[2:0] ADCWORDCLK_SEL[2:0] ADCMCLK_SEL[2:0] |
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