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WM8593 Datasheet(PDF) 68 Page - Wolfson Microelectronics plc |
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WM8593 Datasheet(HTML) 68 Page - Wolfson Microelectronics plc |
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68 / 98 page ![]() WM8593 Product Preview w PP Rev 1.0 January 2007 68 R15 (0Fh) – ADC Control Register 3 (ADC_CTRL3) Bit # 15 14 13 12 11 10 9 8 Read 0 0 0 0 0 0 0 0 Write N/A N/A N/A N/A N/A N/A N/A N/A Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 Write N/A N/A N/A N/A N/A N/A N/A ADC_MSTR Default 0 0 0 0 0 0 0 0 N/A = Not Applicable (no function implemented) Function Description ADC_MSTR ADC Master Mode Select 0 = Slave mode, ADCBCLK and ADCLRCLK are inputs to WM8593 1 = Master mode, ADCBCLK and ADCLRCLK are outputs from WM8593 Figure 39 R15 – ADC Control Register 3 R16 (10h) – Left ADC Digital Volume Control Register (ADCL_VOL) Bit # 15 14 13 12 11 10 9 8 Read 0 0 0 0 0 0 0 Write N/A N/A N/A N/A N/A N/A N/A ADCL_VU Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Read Write ADCL_VOL[7:0] Default 1 1 0 0 0 0 1 1 N/A = Not Applicable (no function implemented) Function Description ADCL_VOL[7:0] Left ADC Digital Volume 0000 0000 = Digital mute 0000 0001 = -97dB 0000 0010 = -96.5dB …0.5dB steps 1100 0011 = 0dB …0.5dB steps 1111 1110 = +29.5dB 1111 1111 = +30dB ADCL_VU Left DAC Digital Volume Update 0 = Latch ADCL_VOL[7:0] into Register Map but do not update volume 1 = Latch ADCL_VOL[7:0] into Register Map and update left and right channels simultaneously Figure 40 R16 – Left ADC Digital Volume Control Register |
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