AT87C5103-ICSIL datasheet(28/64 Pages) ATMEL

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AT8xC5103

4134C–8051–09/04

Mode 0 (13-bit Timer)

Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0

(see Figure 15). The upper three bits of TL0 register are indeterminate and should be

ignored. Prescaler overflow increments TH0 register.

Figure 15. Timer/Counter x (x = 0 or 1) in Mode 0

Mode 1 (16-bit Timer)

Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in

cascade (see Figure 16). The selected input increments TL0 register.

Figure 16. Timer/Counter x (x = 0 or 1) in Mode 1

Mode 2 (8-bit Timer with Auto-

Reload)

Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads

from TH0 register (see Figure 17). TL0 overflow sets TF0 flag in TCON register and

reloads TL0 with the contents of TH0, which is preset by software. When the interrupt

request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next

reload value may be changed at any time by writing it to TH0 register.

Figure 17. Timer/Counter x (x = 0 or 1) in Mode 2

PERIPH

CLOCK

TRx

TCON Reg

TFx

TCON Reg

GATEx

TMOD Reg

÷ 6

Overflow

Timer x

Interrupt

Request

C/Tx#

TMOD Reg

TLx

(5 Bits)

THx

(8 Bits)

INTx#

TRx

TCON Reg

TFx

TCON Reg

GATEx

TMOD Reg

Overflow

Timer x

Interrupt

Request

C/Tx#

TMOD Reg

TLx

(8 Bits)

THx

(8 Bits)

INTx#

PERIPH

CLOCK

÷ 6

TRx

TCON Reg

TFx

TCON Reg

GATEx

TMOD Reg

Overflow

Timer x

Interrupt

Request

C/Tx#

TMOD Reg

TLx

(8 Bits)

THx

(8 Bits)

INTx#

PERIPH

CLOCK

÷ 6

AT87C5103-ICSIL Datasheet(PDF) 28 Page - ATMEL Corporation

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